TRANSISTOR WITH ULTRA-SHORT GATE SHAPE AND MEMORY CELL, AND METHOD OF MANUFACTURING THEM
PROBLEM TO BE SOLVED: To provide a semiconductor element allowing channel length to be dramatically scaled by manufacturing a high-performance transistor and a memory cell exhibiting strong program/erasure efficiency and reading speed, and having a very small gate shape and a total size allowing a l...
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| creator | WANG HSINGYA ARTHUR RABKIN PETER CHOU KAING |
| description | PROBLEM TO BE SOLVED: To provide a semiconductor element allowing channel length to be dramatically scaled by manufacturing a high-performance transistor and a memory cell exhibiting strong program/erasure efficiency and reading speed, and having a very small gate shape and a total size allowing a low operation voltage; and a manufacturing method thereof. SOLUTION: The method of forming a semiconductor transistor includes processes of: forming a gate electrode over but insulated from a semiconductor substrate region 100; forming off-set spacers 110a, 110b along sidewalls of the gate electrode; and forming a source region and a drain region in the substrate region after forming the off-set spacers so that the extent of an overlap between the gate electrode and each of the source and drain regions is dependent on the thickness of the off-set spacers. COPYRIGHT: (C)2010,JPO&INPIT |
| format | Patent |
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SOLUTION: The method of forming a semiconductor transistor includes processes of: forming a gate electrode over but insulated from a semiconductor substrate region 100; forming off-set spacers 110a, 110b along sidewalls of the gate electrode; and forming a source region and a drain region in the substrate region after forming the off-set spacers so that the extent of an overlap between the gate electrode and each of the source and drain regions is dependent on the thickness of the off-set spacers. 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SOLUTION: The method of forming a semiconductor transistor includes processes of: forming a gate electrode over but insulated from a semiconductor substrate region 100; forming off-set spacers 110a, 110b along sidewalls of the gate electrode; and forming a source region and a drain region in the substrate region after forming the off-set spacers so that the extent of an overlap between the gate electrode and each of the source and drain regions is dependent on the thickness of the off-set spacers. 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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | TRANSISTOR WITH ULTRA-SHORT GATE SHAPE AND MEMORY CELL, AND METHOD OF MANUFACTURING THEM |
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