ASSERTION DESCRIPTION LANGUAGE GENERATION METHOD AND DEVICE, AND ASSERTION BASE SIMULATION PROGRAM USING IT
PROBLEM TO BE SOLVED: To prevent deterioration of simulation speed by incorporating a mechanism allowing individual control of in-line added assertion description. SOLUTION: This assertion description language generation method has steps: for reading an input file described by circuit description an...
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| creator | TANAKA HIROSHI INOUE ATSUSHI HASEGAWA YASUYO OTSUJI AKIO OGUSHI ETSUKO TOMIKAWA SEI |
| description | PROBLEM TO BE SOLVED: To prevent deterioration of simulation speed by incorporating a mechanism allowing individual control of in-line added assertion description. SOLUTION: This assertion description language generation method has steps: for reading an input file described by circuit description and the assertion description grouped in each verification function or the like of a target circuit, wherein an identifier is added to a head part of each line of the assertion description; for instructing a group of the function or the like to be performed with operation verification by simulation; for retrieving the assertion description of a corresponding function or the like of the input file based on the instruction; for deleting the identifier of each line of the assertion description of the function or the like made to be a verification target by the retrieval; for changing the identifier of each line of the assertion description made to be out of the verification target by the retrieval into a comment line, or deleting the whole description of each line; and for generating an output file described by the circuit description and the assertion description converted by the deletion or the change. COPYRIGHT: (C)2009,JPO&INPIT |
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SOLUTION: This assertion description language generation method has steps: for reading an input file described by circuit description and the assertion description grouped in each verification function or the like of a target circuit, wherein an identifier is added to a head part of each line of the assertion description; for instructing a group of the function or the like to be performed with operation verification by simulation; for retrieving the assertion description of a corresponding function or the like of the input file based on the instruction; for deleting the identifier of each line of the assertion description of the function or the like made to be a verification target by the retrieval; for changing the identifier of each line of the assertion description made to be out of the verification target by the retrieval into a comment line, or deleting the whole description of each line; and for generating an output file described by the circuit description and the assertion description converted by the deletion or the change. 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SOLUTION: This assertion description language generation method has steps: for reading an input file described by circuit description and the assertion description grouped in each verification function or the like of a target circuit, wherein an identifier is added to a head part of each line of the assertion description; for instructing a group of the function or the like to be performed with operation verification by simulation; for retrieving the assertion description of a corresponding function or the like of the input file based on the instruction; for deleting the identifier of each line of the assertion description of the function or the like made to be a verification target by the retrieval; for changing the identifier of each line of the assertion description made to be out of the verification target by the retrieval into a comment line, or deleting the whole description of each line; and for generating an output file described by the circuit description and the assertion description converted by the deletion or the change. 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SOLUTION: This assertion description language generation method has steps: for reading an input file described by circuit description and the assertion description grouped in each verification function or the like of a target circuit, wherein an identifier is added to a head part of each line of the assertion description; for instructing a group of the function or the like to be performed with operation verification by simulation; for retrieving the assertion description of a corresponding function or the like of the input file based on the instruction; for deleting the identifier of each line of the assertion description of the function or the like made to be a verification target by the retrieval; for changing the identifier of each line of the assertion description made to be out of the verification target by the retrieval into a comment line, or deleting the whole description of each line; and for generating an output file described by the circuit description and the assertion description converted by the deletion or the change. COPYRIGHT: (C)2009,JPO&INPIT</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | ASSERTION DESCRIPTION LANGUAGE GENERATION METHOD AND DEVICE, AND ASSERTION BASE SIMULATION PROGRAM USING IT |
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