LOGIC VERIFICATION SUPPORT SYSTEM

PROBLEM TO BE SOLVED: To provide a logic verification support system for detecting an inconsistent place in a state transition graph of a logic circuit, for storing a temporarily detected inconsistent place in a storage area, and for clearly describing even a state which should not exist as an opera...

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1. Verfasser: SHOJI MINORU
Format: Patent
Sprache:eng
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Zusammenfassung:PROBLEM TO BE SOLVED: To provide a logic verification support system for detecting an inconsistent place in a state transition graph of a logic circuit, for storing a temporarily detected inconsistent place in a storage area, and for clearly describing even a state which should not exist as an operation as a verification item. SOLUTION: This logic verification support system for preparing verification items for verifying a logic circuit has an inconsistency extraction means for, when transition conditions shown by state transition information showing transition from a transition source state to a transition destination state are included in the transition conditions of the other state transition information, extracting it as an inconsistent place for each state information showing the logic circuit in the operation of the logic circuit. COPYRIGHT: (C)2008,JPO&INPIT