METHOD FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

PROBLEM TO BE SOLVED: To provide a technology which can elevate the reliability of a semiconductor integrated circuit device. SOLUTION: In a wafer manufacturing stage, a visual inspection of a semiconductor integrated circuit device WPP100, on both sides of whose bump a rewiring layer is formed, is...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: AKAIWA MASAYASU
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator AKAIWA MASAYASU
description PROBLEM TO BE SOLVED: To provide a technology which can elevate the reliability of a semiconductor integrated circuit device. SOLUTION: In a wafer manufacturing stage, a visual inspection of a semiconductor integrated circuit device WPP100, on both sides of whose bump a rewiring layer is formed, is conducted in a manner such that a process which takes a picture of it by a camera 202 irradiating light from a coaxially down-irradiating illuminator 204 in a coaxially down-irradiating direction and a process which takes a picture of it by a camera 202 irradiating light from a diffusion illuminator 205 in a direction crossing the taking-a-photo direction are changed in order, and a pattern matching is conducted between a previously obtained image and a previously pictured teaching image, thereby, it is determined whether there is a defect. COPYRIGHT: (C)2008,JPO&INPIT
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2008085252A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2008085252A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2008085252A3</originalsourceid><addsrcrecordid>eNrjZHDwdQ3x8HdRcPMPUvB19At1c3QOCQ3y9HNXCHb19XT293MJdQ4Bynn6hbi6BzmGuLooOHsGOYd6hii4uIZ5OrvyMLCmJeYUp_JCaW4GJTfXEGcP3dSC_PjU4oLE5NS81JJ4rwAjAwMLAwtTI1MjR2OiFAEAI6MrYA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>METHOD FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE</title><source>esp@cenet</source><creator>AKAIWA MASAYASU</creator><creatorcontrib>AKAIWA MASAYASU</creatorcontrib><description>PROBLEM TO BE SOLVED: To provide a technology which can elevate the reliability of a semiconductor integrated circuit device. SOLUTION: In a wafer manufacturing stage, a visual inspection of a semiconductor integrated circuit device WPP100, on both sides of whose bump a rewiring layer is formed, is conducted in a manner such that a process which takes a picture of it by a camera 202 irradiating light from a coaxially down-irradiating illuminator 204 in a coaxially down-irradiating direction and a process which takes a picture of it by a camera 202 irradiating light from a diffusion illuminator 205 in a direction crossing the taking-a-photo direction are changed in order, and a pattern matching is conducted between a previously obtained image and a previously pictured teaching image, thereby, it is determined whether there is a defect. COPYRIGHT: (C)2008,JPO&amp;INPIT</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIRCHEMICAL OR PHYSICAL PROPERTIES ; MEASURING ; MEASURING ANGLES ; MEASURING AREAS ; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS ; MEASURING LENGTH, THICKNESS OR SIMILAR LINEARDIMENSIONS ; PHYSICS ; SEMICONDUCTOR DEVICES ; TESTING</subject><creationdate>2008</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20080410&amp;DB=EPODOC&amp;CC=JP&amp;NR=2008085252A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76318</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20080410&amp;DB=EPODOC&amp;CC=JP&amp;NR=2008085252A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>AKAIWA MASAYASU</creatorcontrib><title>METHOD FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE</title><description>PROBLEM TO BE SOLVED: To provide a technology which can elevate the reliability of a semiconductor integrated circuit device. SOLUTION: In a wafer manufacturing stage, a visual inspection of a semiconductor integrated circuit device WPP100, on both sides of whose bump a rewiring layer is formed, is conducted in a manner such that a process which takes a picture of it by a camera 202 irradiating light from a coaxially down-irradiating illuminator 204 in a coaxially down-irradiating direction and a process which takes a picture of it by a camera 202 irradiating light from a diffusion illuminator 205 in a direction crossing the taking-a-photo direction are changed in order, and a pattern matching is conducted between a previously obtained image and a previously pictured teaching image, thereby, it is determined whether there is a defect. COPYRIGHT: (C)2008,JPO&amp;INPIT</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIRCHEMICAL OR PHYSICAL PROPERTIES</subject><subject>MEASURING</subject><subject>MEASURING ANGLES</subject><subject>MEASURING AREAS</subject><subject>MEASURING IRREGULARITIES OF SURFACES OR CONTOURS</subject><subject>MEASURING LENGTH, THICKNESS OR SIMILAR LINEARDIMENSIONS</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>TESTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2008</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHDwdQ3x8HdRcPMPUvB19At1c3QOCQ3y9HNXCHb19XT293MJdQ4Bynn6hbi6BzmGuLooOHsGOYd6hii4uIZ5OrvyMLCmJeYUp_JCaW4GJTfXEGcP3dSC_PjU4oLE5NS81JJ4rwAjAwMLAwtTI1MjR2OiFAEAI6MrYA</recordid><startdate>20080410</startdate><enddate>20080410</enddate><creator>AKAIWA MASAYASU</creator><scope>EVB</scope></search><sort><creationdate>20080410</creationdate><title>METHOD FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE</title><author>AKAIWA MASAYASU</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2008085252A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2008</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIRCHEMICAL OR PHYSICAL PROPERTIES</topic><topic>MEASURING</topic><topic>MEASURING ANGLES</topic><topic>MEASURING AREAS</topic><topic>MEASURING IRREGULARITIES OF SURFACES OR CONTOURS</topic><topic>MEASURING LENGTH, THICKNESS OR SIMILAR LINEARDIMENSIONS</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>TESTING</topic><toplevel>online_resources</toplevel><creatorcontrib>AKAIWA MASAYASU</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>AKAIWA MASAYASU</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>METHOD FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE</title><date>2008-04-10</date><risdate>2008</risdate><abstract>PROBLEM TO BE SOLVED: To provide a technology which can elevate the reliability of a semiconductor integrated circuit device. SOLUTION: In a wafer manufacturing stage, a visual inspection of a semiconductor integrated circuit device WPP100, on both sides of whose bump a rewiring layer is formed, is conducted in a manner such that a process which takes a picture of it by a camera 202 irradiating light from a coaxially down-irradiating illuminator 204 in a coaxially down-irradiating direction and a process which takes a picture of it by a camera 202 irradiating light from a diffusion illuminator 205 in a direction crossing the taking-a-photo direction are changed in order, and a pattern matching is conducted between a previously obtained image and a previously pictured teaching image, thereby, it is determined whether there is a defect. COPYRIGHT: (C)2008,JPO&amp;INPIT</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_JP2008085252A
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIRCHEMICAL OR PHYSICAL PROPERTIES
MEASURING
MEASURING ANGLES
MEASURING AREAS
MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
MEASURING LENGTH, THICKNESS OR SIMILAR LINEARDIMENSIONS
PHYSICS
SEMICONDUCTOR DEVICES
TESTING
title METHOD FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-10T21%3A08%3A03IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=AKAIWA%20MASAYASU&rft.date=2008-04-10&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJP2008085252A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true