MANUFACTURING METHOD OF CIRCUIT BOARD

PROBLEM TO BE SOLVED: To provide a manufacturing method of a circuit board capable of reducing the failure of insulated breakdown voltage between adjoining wiring, while materializing the microfabrication of the processing size of wiring. SOLUTION: An insulating layer 3 is formed on a board 1. Next,...

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Hauptverfasser: MIZUHARA HIDEKI, NAKAZATO MAYUMI
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creator MIZUHARA HIDEKI
NAKAZATO MAYUMI
description PROBLEM TO BE SOLVED: To provide a manufacturing method of a circuit board capable of reducing the failure of insulated breakdown voltage between adjoining wiring, while materializing the microfabrication of the processing size of wiring. SOLUTION: An insulating layer 3 is formed on a board 1. Next, a conductor 4a and a conductor 4b adjoining the conductor 4a are formed on the surface of the insulating layer 3, and at least a side surface of the upper part of the conductor 4a and the conductor 4b is processed into a forward tapered shape profile. Then, by press fitting the conductor 4a and the conductor 4b into the insulating layer 3, the conductor 4a and the conductor 4b are arranged into the insulating layer 3 in a self-adjusting way. Consequently, the insulating layer 3 is formed between the conductor 4a and the conductor 4b having a convex shape 3a, and also a region 5 which does not come into contact with the insulating layer 3 is formed in the side of the conductor 4a (the side of the conductor 4b). COPYRIGHT: (C)2008,JPO&INPIT
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2008034722A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2008034722A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2008034722A3</originalsourceid><addsrcrecordid>eNrjZFD1dfQLdXN0DgkN8vRzV_B1DfHwd1Hwd1Nw9gxyDvUMUXDydwxy4WFgTUvMKU7lhdLcDEpuriHOHrqpBfnxqcUFicmpeakl8V4BRgYGFgbGJuZGRo7GRCkCAOAMI50</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>MANUFACTURING METHOD OF CIRCUIT BOARD</title><source>esp@cenet</source><creator>MIZUHARA HIDEKI ; NAKAZATO MAYUMI</creator><creatorcontrib>MIZUHARA HIDEKI ; NAKAZATO MAYUMI</creatorcontrib><description>PROBLEM TO BE SOLVED: To provide a manufacturing method of a circuit board capable of reducing the failure of insulated breakdown voltage between adjoining wiring, while materializing the microfabrication of the processing size of wiring. SOLUTION: An insulating layer 3 is formed on a board 1. Next, a conductor 4a and a conductor 4b adjoining the conductor 4a are formed on the surface of the insulating layer 3, and at least a side surface of the upper part of the conductor 4a and the conductor 4b is processed into a forward tapered shape profile. Then, by press fitting the conductor 4a and the conductor 4b into the insulating layer 3, the conductor 4a and the conductor 4b are arranged into the insulating layer 3 in a self-adjusting way. Consequently, the insulating layer 3 is formed between the conductor 4a and the conductor 4b having a convex shape 3a, and also a region 5 which does not come into contact with the insulating layer 3 is formed in the side of the conductor 4a (the side of the conductor 4b). COPYRIGHT: (C)2008,JPO&amp;INPIT</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; PRINTED CIRCUITS ; SEMICONDUCTOR DEVICES</subject><creationdate>2008</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20080214&amp;DB=EPODOC&amp;CC=JP&amp;NR=2008034722A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20080214&amp;DB=EPODOC&amp;CC=JP&amp;NR=2008034722A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MIZUHARA HIDEKI</creatorcontrib><creatorcontrib>NAKAZATO MAYUMI</creatorcontrib><title>MANUFACTURING METHOD OF CIRCUIT BOARD</title><description>PROBLEM TO BE SOLVED: To provide a manufacturing method of a circuit board capable of reducing the failure of insulated breakdown voltage between adjoining wiring, while materializing the microfabrication of the processing size of wiring. SOLUTION: An insulating layer 3 is formed on a board 1. Next, a conductor 4a and a conductor 4b adjoining the conductor 4a are formed on the surface of the insulating layer 3, and at least a side surface of the upper part of the conductor 4a and the conductor 4b is processed into a forward tapered shape profile. Then, by press fitting the conductor 4a and the conductor 4b into the insulating layer 3, the conductor 4a and the conductor 4b are arranged into the insulating layer 3 in a self-adjusting way. Consequently, the insulating layer 3 is formed between the conductor 4a and the conductor 4b having a convex shape 3a, and also a region 5 which does not come into contact with the insulating layer 3 is formed in the side of the conductor 4a (the side of the conductor 4b). COPYRIGHT: (C)2008,JPO&amp;INPIT</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>PRINTED CIRCUITS</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2008</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFD1dfQLdXN0DgkN8vRzV_B1DfHwd1Hwd1Nw9gxyDvUMUXDydwxy4WFgTUvMKU7lhdLcDEpuriHOHrqpBfnxqcUFicmpeakl8V4BRgYGFgbGJuZGRo7GRCkCAOAMI50</recordid><startdate>20080214</startdate><enddate>20080214</enddate><creator>MIZUHARA HIDEKI</creator><creator>NAKAZATO MAYUMI</creator><scope>EVB</scope></search><sort><creationdate>20080214</creationdate><title>MANUFACTURING METHOD OF CIRCUIT BOARD</title><author>MIZUHARA HIDEKI ; NAKAZATO MAYUMI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2008034722A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2008</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>PRINTED CIRCUITS</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>MIZUHARA HIDEKI</creatorcontrib><creatorcontrib>NAKAZATO MAYUMI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MIZUHARA HIDEKI</au><au>NAKAZATO MAYUMI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>MANUFACTURING METHOD OF CIRCUIT BOARD</title><date>2008-02-14</date><risdate>2008</risdate><abstract>PROBLEM TO BE SOLVED: To provide a manufacturing method of a circuit board capable of reducing the failure of insulated breakdown voltage between adjoining wiring, while materializing the microfabrication of the processing size of wiring. SOLUTION: An insulating layer 3 is formed on a board 1. Next, a conductor 4a and a conductor 4b adjoining the conductor 4a are formed on the surface of the insulating layer 3, and at least a side surface of the upper part of the conductor 4a and the conductor 4b is processed into a forward tapered shape profile. Then, by press fitting the conductor 4a and the conductor 4b into the insulating layer 3, the conductor 4a and the conductor 4b are arranged into the insulating layer 3 in a self-adjusting way. Consequently, the insulating layer 3 is formed between the conductor 4a and the conductor 4b having a convex shape 3a, and also a region 5 which does not come into contact with the insulating layer 3 is formed in the side of the conductor 4a (the side of the conductor 4b). COPYRIGHT: (C)2008,JPO&amp;INPIT</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
PRINTED CIRCUITS
SEMICONDUCTOR DEVICES
title MANUFACTURING METHOD OF CIRCUIT BOARD
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-28T22%3A05%3A42IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=MIZUHARA%20HIDEKI&rft.date=2008-02-14&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJP2008034722A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true