BIAS CIRCUIT FOR POWER AMPLIFIER

BIAS CIRCUIT FOR POWER AMPLIFIER

PROBLEM TO BE SOLVED: To provide a technology of preventing an idle current from unflowing when a reference voltage Vref is lowered in a GaAs-HBT power amplifier. SOLUTION: The technology disclosed herein adopts a configuration, wherein a resistor Rbb9 is provided in parallel with a voltage drive bi...

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Hauptverfasser: YAMAMOTO KAZUYA, MAEMURA KIMIMASA
Format: Patent
Sprache:eng
Schlagworte:
AMPLIFIERS
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
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creator YAMAMOTO KAZUYA
MAEMURA KIMIMASA
description PROBLEM TO BE SOLVED: To provide a technology of preventing an idle current from unflowing when a reference voltage Vref is lowered in a GaAs-HBT power amplifier. SOLUTION: The technology disclosed herein adopts a configuration, wherein a resistor Rbb9 is provided in parallel with a voltage drive bias circuit including a transistor (GaAs-HBT) Trb1. According to this configuration, in an idle state a voltage applied by a reference input terminal (Vrefb) is lower than the operating voltage of a Trb4, a current is supplied to the base terminal of a TR2 via the resistor Rbb9 from the Vrefb. Thus, even if the reference voltage Vref is decreased to less than twice the barrier voltage of the HBTs employed in the bias circuit, the power amplifier can attain desired amplification operations, while keeping the idle current nearly constant, from low up to high temperatures. COPYRIGHT: (C)2007,JPO&INPIT
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2007134768A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2007134768A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2007134768A3</originalsourceid><addsrcrecordid>eNrjZFBw8nQMVnD2DHIO9QxRcPMPUgjwD3cNUnD0DfDxdPN0DeJhYE1LzClO5YXS3AxKbq4hzh66qQX58anFBYnJqXmpJfFeAUYGBuaGxibmZhaOxkQpAgAq5iJG</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>BIAS CIRCUIT FOR POWER AMPLIFIER</title><source>esp@cenet</source><creator>YAMAMOTO KAZUYA ; MAEMURA KIMIMASA</creator><creatorcontrib>YAMAMOTO KAZUYA ; MAEMURA KIMIMASA</creatorcontrib><description>PROBLEM TO BE SOLVED: To provide a technology of preventing an idle current from unflowing when a reference voltage Vref is lowered in a GaAs-HBT power amplifier. SOLUTION: The technology disclosed herein adopts a configuration, wherein a resistor Rbb9 is provided in parallel with a voltage drive bias circuit including a transistor (GaAs-HBT) Trb1. According to this configuration, in an idle state a voltage applied by a reference input terminal (Vrefb) is lower than the operating voltage of a Trb4, a current is supplied to the base terminal of a TR2 via the resistor Rbb9 from the Vrefb. Thus, even if the reference voltage Vref is decreased to less than twice the barrier voltage of the HBTs employed in the bias circuit, the power amplifier can attain desired amplification operations, while keeping the idle current nearly constant, from low up to high temperatures. COPYRIGHT: (C)2007,JPO&amp;INPIT</description><language>eng</language><subject>AMPLIFIERS ; BASIC ELECTRONIC CIRCUITRY ; ELECTRICITY</subject><creationdate>2007</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20070531&amp;DB=EPODOC&amp;CC=JP&amp;NR=2007134768A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20070531&amp;DB=EPODOC&amp;CC=JP&amp;NR=2007134768A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>YAMAMOTO KAZUYA</creatorcontrib><creatorcontrib>MAEMURA KIMIMASA</creatorcontrib><title>BIAS CIRCUIT FOR POWER AMPLIFIER</title><description>PROBLEM TO BE SOLVED: To provide a technology of preventing an idle current from unflowing when a reference voltage Vref is lowered in a GaAs-HBT power amplifier. SOLUTION: The technology disclosed herein adopts a configuration, wherein a resistor Rbb9 is provided in parallel with a voltage drive bias circuit including a transistor (GaAs-HBT) Trb1. According to this configuration, in an idle state a voltage applied by a reference input terminal (Vrefb) is lower than the operating voltage of a Trb4, a current is supplied to the base terminal of a TR2 via the resistor Rbb9 from the Vrefb. Thus, even if the reference voltage Vref is decreased to less than twice the barrier voltage of the HBTs employed in the bias circuit, the power amplifier can attain desired amplification operations, while keeping the idle current nearly constant, from low up to high temperatures. COPYRIGHT: (C)2007,JPO&amp;INPIT</description><subject>AMPLIFIERS</subject><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRICITY</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2007</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFBw8nQMVnD2DHIO9QxRcPMPUgjwD3cNUnD0DfDxdPN0DeJhYE1LzClO5YXS3AxKbq4hzh66qQX58anFBYnJqXmpJfFeAUYGBuaGxibmZhaOxkQpAgAq5iJG</recordid><startdate>20070531</startdate><enddate>20070531</enddate><creator>YAMAMOTO KAZUYA</creator><creator>MAEMURA KIMIMASA</creator><scope>EVB</scope></search><sort><creationdate>20070531</creationdate><title>BIAS CIRCUIT FOR POWER AMPLIFIER</title><author>YAMAMOTO KAZUYA ; MAEMURA KIMIMASA</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2007134768A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2007</creationdate><topic>AMPLIFIERS</topic><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>ELECTRICITY</topic><toplevel>online_resources</toplevel><creatorcontrib>YAMAMOTO KAZUYA</creatorcontrib><creatorcontrib>MAEMURA KIMIMASA</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>YAMAMOTO KAZUYA</au><au>MAEMURA KIMIMASA</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>BIAS CIRCUIT FOR POWER AMPLIFIER</title><date>2007-05-31</date><risdate>2007</risdate><abstract>PROBLEM TO BE SOLVED: To provide a technology of preventing an idle current from unflowing when a reference voltage Vref is lowered in a GaAs-HBT power amplifier. SOLUTION: The technology disclosed herein adopts a configuration, wherein a resistor Rbb9 is provided in parallel with a voltage drive bias circuit including a transistor (GaAs-HBT) Trb1. According to this configuration, in an idle state a voltage applied by a reference input terminal (Vrefb) is lower than the operating voltage of a Trb4, a current is supplied to the base terminal of a TR2 via the resistor Rbb9 from the Vrefb. Thus, even if the reference voltage Vref is decreased to less than twice the barrier voltage of the HBTs employed in the bias circuit, the power amplifier can attain desired amplification operations, while keeping the idle current nearly constant, from low up to high temperatures. COPYRIGHT: (C)2007,JPO&amp;INPIT</abstract><oa>free_for_read</oa></addata></record>
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subjects AMPLIFIERS
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
title BIAS CIRCUIT FOR POWER AMPLIFIER
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