CLOCK CIRCUIT

PROBLEM TO BE SOLVED: To provide a clock circuit capable of preventing through-current. SOLUTION: This clock circuit comprises a clock signal supply circuit 10, logic gates AND1 and AND2 connected thereto, a multistage clock driver circuits B2-B11 connected thereto, clock signal supplied circuits 13-18 connected to the final stage, and control circuits 11 and 12 inputting control signals to the logic gates AND1 and AND2. Each of the clock driver circuits B1-B22 includes first inverter circuits INV1 and INV2 of a CMOS inverter circuit structure and an amplitude control circuit CT1. The first inverter circuit INV1 is provided with a p-type FET (P1) for applying voltage higher than high-potential side power supply voltage VDD to a substrate. The amplitude control circuit CT1 includes two n-type FETs (N3 and N4). COPYRIGHT: (C)2007,JPO&INPIT