NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

PROBLEM TO BE SOLVED: To improve the reliability of a memory cell by controlling charge trapping during writing and erasing, and suppressing variance in threshold voltage in charge holding state due to detrap. SOLUTION: The nonvolatile semiconductor memory device is provided with a floating gate ele...

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Hauptverfasser: YASUDA NAOKI, MURAOKA KOICHI, NISHIKAWA YUKIE, NISHINO HIROTAKE, KIKUCHI SACHIKO
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creator YASUDA NAOKI
MURAOKA KOICHI
NISHIKAWA YUKIE
NISHINO HIROTAKE
KIKUCHI SACHIKO
description PROBLEM TO BE SOLVED: To improve the reliability of a memory cell by controlling charge trapping during writing and erasing, and suppressing variance in threshold voltage in charge holding state due to detrap. SOLUTION: The nonvolatile semiconductor memory device is provided with a floating gate electrode 12 which is selectively formed on the main surface of a first conductive type semiconductor substrate 10 with a tunnel insulating film 11 in-between, a control gate electrode 14 which is formed on the floating gate electrode 12 with an insulating film 13 between electrodes made of a high dielectric material in-between, and a second conductive type source/drain area 16 formed on the main surface of the semiconductor substrate 10. In this case, either of the boundary surface of the control gate electrode 14 with at least the insulating film 13 between electrodes or the boundary surface of the floating gate electrode 12 with at least the insulating film 13 between electrodes is formed of a p-type semiconductor layer containing at least either of Si and Ge, and the other is formed of an n-type Si or metal-based conductive material. COPYRIGHT: (C)2007,JPO&INPIT
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2007053171A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2007053171A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2007053171A3</originalsourceid><addsrcrecordid>eNrjZFD38_cL8_dxDPH0cVUIdvX1dPb3cwl1DvEPUvB19fUPilRwcQ3zdHblYWBNS8wpTuWF0twMSm6uIc4euqkF-fGpxQWJyal5qSXxXgFGBgbmBqbGhuaGjsZEKQIAUXIkiQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>NONVOLATILE SEMICONDUCTOR MEMORY DEVICE</title><source>esp@cenet</source><creator>YASUDA NAOKI ; MURAOKA KOICHI ; NISHIKAWA YUKIE ; NISHINO HIROTAKE ; KIKUCHI SACHIKO</creator><creatorcontrib>YASUDA NAOKI ; MURAOKA KOICHI ; NISHIKAWA YUKIE ; NISHINO HIROTAKE ; KIKUCHI SACHIKO</creatorcontrib><description>PROBLEM TO BE SOLVED: To improve the reliability of a memory cell by controlling charge trapping during writing and erasing, and suppressing variance in threshold voltage in charge holding state due to detrap. SOLUTION: The nonvolatile semiconductor memory device is provided with a floating gate electrode 12 which is selectively formed on the main surface of a first conductive type semiconductor substrate 10 with a tunnel insulating film 11 in-between, a control gate electrode 14 which is formed on the floating gate electrode 12 with an insulating film 13 between electrodes made of a high dielectric material in-between, and a second conductive type source/drain area 16 formed on the main surface of the semiconductor substrate 10. In this case, either of the boundary surface of the control gate electrode 14 with at least the insulating film 13 between electrodes or the boundary surface of the floating gate electrode 12 with at least the insulating film 13 between electrodes is formed of a p-type semiconductor layer containing at least either of Si and Ge, and the other is formed of an n-type Si or metal-based conductive material. COPYRIGHT: (C)2007,JPO&amp;INPIT</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2007</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20070301&amp;DB=EPODOC&amp;CC=JP&amp;NR=2007053171A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76419</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20070301&amp;DB=EPODOC&amp;CC=JP&amp;NR=2007053171A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>YASUDA NAOKI</creatorcontrib><creatorcontrib>MURAOKA KOICHI</creatorcontrib><creatorcontrib>NISHIKAWA YUKIE</creatorcontrib><creatorcontrib>NISHINO HIROTAKE</creatorcontrib><creatorcontrib>KIKUCHI SACHIKO</creatorcontrib><title>NONVOLATILE SEMICONDUCTOR MEMORY DEVICE</title><description>PROBLEM TO BE SOLVED: To improve the reliability of a memory cell by controlling charge trapping during writing and erasing, and suppressing variance in threshold voltage in charge holding state due to detrap. SOLUTION: The nonvolatile semiconductor memory device is provided with a floating gate electrode 12 which is selectively formed on the main surface of a first conductive type semiconductor substrate 10 with a tunnel insulating film 11 in-between, a control gate electrode 14 which is formed on the floating gate electrode 12 with an insulating film 13 between electrodes made of a high dielectric material in-between, and a second conductive type source/drain area 16 formed on the main surface of the semiconductor substrate 10. In this case, either of the boundary surface of the control gate electrode 14 with at least the insulating film 13 between electrodes or the boundary surface of the floating gate electrode 12 with at least the insulating film 13 between electrodes is formed of a p-type semiconductor layer containing at least either of Si and Ge, and the other is formed of an n-type Si or metal-based conductive material. COPYRIGHT: (C)2007,JPO&amp;INPIT</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2007</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFD38_cL8_dxDPH0cVUIdvX1dPb3cwl1DvEPUvB19fUPilRwcQ3zdHblYWBNS8wpTuWF0twMSm6uIc4euqkF-fGpxQWJyal5qSXxXgFGBgbmBqbGhuaGjsZEKQIAUXIkiQ</recordid><startdate>20070301</startdate><enddate>20070301</enddate><creator>YASUDA NAOKI</creator><creator>MURAOKA KOICHI</creator><creator>NISHIKAWA YUKIE</creator><creator>NISHINO HIROTAKE</creator><creator>KIKUCHI SACHIKO</creator><scope>EVB</scope></search><sort><creationdate>20070301</creationdate><title>NONVOLATILE SEMICONDUCTOR MEMORY DEVICE</title><author>YASUDA NAOKI ; MURAOKA KOICHI ; NISHIKAWA YUKIE ; NISHINO HIROTAKE ; KIKUCHI SACHIKO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2007053171A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2007</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>YASUDA NAOKI</creatorcontrib><creatorcontrib>MURAOKA KOICHI</creatorcontrib><creatorcontrib>NISHIKAWA YUKIE</creatorcontrib><creatorcontrib>NISHINO HIROTAKE</creatorcontrib><creatorcontrib>KIKUCHI SACHIKO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>YASUDA NAOKI</au><au>MURAOKA KOICHI</au><au>NISHIKAWA YUKIE</au><au>NISHINO HIROTAKE</au><au>KIKUCHI SACHIKO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>NONVOLATILE SEMICONDUCTOR MEMORY DEVICE</title><date>2007-03-01</date><risdate>2007</risdate><abstract>PROBLEM TO BE SOLVED: To improve the reliability of a memory cell by controlling charge trapping during writing and erasing, and suppressing variance in threshold voltage in charge holding state due to detrap. SOLUTION: The nonvolatile semiconductor memory device is provided with a floating gate electrode 12 which is selectively formed on the main surface of a first conductive type semiconductor substrate 10 with a tunnel insulating film 11 in-between, a control gate electrode 14 which is formed on the floating gate electrode 12 with an insulating film 13 between electrodes made of a high dielectric material in-between, and a second conductive type source/drain area 16 formed on the main surface of the semiconductor substrate 10. In this case, either of the boundary surface of the control gate electrode 14 with at least the insulating film 13 between electrodes or the boundary surface of the floating gate electrode 12 with at least the insulating film 13 between electrodes is formed of a p-type semiconductor layer containing at least either of Si and Ge, and the other is formed of an n-type Si or metal-based conductive material. COPYRIGHT: (C)2007,JPO&amp;INPIT</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
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