APPLICATION SPECIFIC INTEGRATED CIRCUIT WITH SPACED SPARE LOGIC GATE SUBGROUP, AND MANUFACTURING METHOD THEREOF
PROBLEM TO BE SOLVED: To provide a configuration for enabling a repair tool to access the wiring of a spare logic located on the innermost layer in an application specific integrated circuit (ASIC) having a plurality of metal layers. SOLUTION: The ASIC 10 includes a substrate layer 30, at least one...
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| creator | YU HENRY C SHARP NOLAN DAVID |
| description | PROBLEM TO BE SOLVED: To provide a configuration for enabling a repair tool to access the wiring of a spare logic located on the innermost layer in an application specific integrated circuit (ASIC) having a plurality of metal layers. SOLUTION: The ASIC 10 includes a substrate layer 30, at least one metal layer 32, and an operational block 14. The metal layer 32 is formed above the substrate layer 30. The operational block 14 is formed in the substrate layer 30 and the metal layer 32, and is definable by a two-dimensional boundary 16. The operational block 14 includes a plurality of operational logic gates 20; a first subgroup 22 of spare logic gates; a second subgroup 24 of spare logic gates; operational wiring 40; and spare gate wiring 42. The operational logic gates 20, the first subgroup 22, and the second subgroup 24 are formed on the substrate layer, with the first subgroup 22 being spaced from the second subgroup 24. COPYRIGHT: (C)2007,JPO&INPIT |
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| subjects | BASIC ELECTRIC ELEMENTS CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY PHYSICS SEMICONDUCTOR DEVICES |
| title | APPLICATION SPECIFIC INTEGRATED CIRCUIT WITH SPACED SPARE LOGIC GATE SUBGROUP, AND MANUFACTURING METHOD THEREOF |
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