SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
PROBLEM TO BE SOLVED: To achieve low resistance of a source/drain layer and suppress a short channel effect while suppressing junction leak. SOLUTION: A source layer 18a consisting of an alloy layer having a bottom surface contacting an insulation layer 12 is arranged on one side of a gate electrode...
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creator | WATANABE YUKIMUNE UDA SHINJI MISE NOBUYUKI |
description | PROBLEM TO BE SOLVED: To achieve low resistance of a source/drain layer and suppress a short channel effect while suppressing junction leak. SOLUTION: A source layer 18a consisting of an alloy layer having a bottom surface contacting an insulation layer 12 is arranged on one side of a gate electrode 15. A junction surface to a channel region 17 is formed along a crystal orientation surface 20a of a single crystal semiconductor layer 13. A drain layer 18b consisting of an alloy layer having a bottom surface contacting the insulation layer 12 is formed on the other side of the gate electrode 15. A junction surface to the channel region 17 is formed along a crystal orientation surface 20b of the single crystal semiconductor layer 13. An impurity introducing layer 19a formed in self alignment along the crystal orientation surface 20a is provided on the interface between the alloy layer forming the source layer 18a and the semiconductor layer 13. An impurity introducing layer 19b formed in self alignment along the crystal orientation surface 20b is provided on the interface between the alloy layer forming the drain layer 18b and the semiconductor layer 13. COPYRIGHT: (C)2007,JPO&INPIT |
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SOLUTION: A source layer 18a consisting of an alloy layer having a bottom surface contacting an insulation layer 12 is arranged on one side of a gate electrode 15. A junction surface to a channel region 17 is formed along a crystal orientation surface 20a of a single crystal semiconductor layer 13. A drain layer 18b consisting of an alloy layer having a bottom surface contacting the insulation layer 12 is formed on the other side of the gate electrode 15. A junction surface to the channel region 17 is formed along a crystal orientation surface 20b of the single crystal semiconductor layer 13. An impurity introducing layer 19a formed in self alignment along the crystal orientation surface 20a is provided on the interface between the alloy layer forming the source layer 18a and the semiconductor layer 13. An impurity introducing layer 19b formed in self alignment along the crystal orientation surface 20b is provided on the interface between the alloy layer forming the drain layer 18b and the semiconductor layer 13. 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An impurity introducing layer 19b formed in self alignment along the crystal orientation surface 20b is provided on the interface between the alloy layer forming the drain layer 18b and the semiconductor layer 13. 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An impurity introducing layer 19b formed in self alignment along the crystal orientation surface 20b is provided on the interface between the alloy layer forming the drain layer 18b and the semiconductor layer 13. COPYRIGHT: (C)2007,JPO&INPIT</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE |
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