SEMICONDUCTOR INTEGRATED CIRCUIT AND ITS TEST METHOD
PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of imparting both levels "L" and "H" to a subsequent logic circuit when an analog circuit is set in a power-down state. SOLUTION: A latch circuit 30 is provided between the output side of the analog circu...
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| creator | KONO HARUMI |
| description | PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of imparting both levels "L" and "H" to a subsequent logic circuit when an analog circuit is set in a power-down state. SOLUTION: A latch circuit 30 is provided between the output side of the analog circuit 10 whose operation is controlled by a power-down signal PD and the input side of the logic circuit 20, and the latch circuit 30 is controlled by the power-down signal PD. In the state where the power-down signal PD is set in the "H" state and the analog circuit 10 is set in the operation state, and a signal S10 of a desired level is output, the power-down signal PD is switched into the "L" state. Accordingly, the operation of the analog circuit 10 is stopped and the signal S10 is set always in the "H" state. The signal S10 of the analog circuit 10 just before the power-down signal PD is switched into the "L" state is held in the latch circuit 30, and imparted to the logic circuit 20 as a signal S30. COPYRIGHT: (C)2007,JPO&INPIT |
| format | Patent |
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SOLUTION: A latch circuit 30 is provided between the output side of the analog circuit 10 whose operation is controlled by a power-down signal PD and the input side of the logic circuit 20, and the latch circuit 30 is controlled by the power-down signal PD. In the state where the power-down signal PD is set in the "H" state and the analog circuit 10 is set in the operation state, and a signal S10 of a desired level is output, the power-down signal PD is switched into the "L" state. Accordingly, the operation of the analog circuit 10 is stopped and the signal S10 is set always in the "H" state. The signal S10 of the analog circuit 10 just before the power-down signal PD is switched into the "L" state is held in the latch circuit 30, and imparted to the logic circuit 20 as a signal S30. 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SOLUTION: A latch circuit 30 is provided between the output side of the analog circuit 10 whose operation is controlled by a power-down signal PD and the input side of the logic circuit 20, and the latch circuit 30 is controlled by the power-down signal PD. In the state where the power-down signal PD is set in the "H" state and the analog circuit 10 is set in the operation state, and a signal S10 of a desired level is output, the power-down signal PD is switched into the "L" state. Accordingly, the operation of the analog circuit 10 is stopped and the signal S10 is set always in the "H" state. The signal S10 of the analog circuit 10 just before the power-down signal PD is switched into the "L" state is held in the latch circuit 30, and imparted to the logic circuit 20 as a signal S30. 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SOLUTION: A latch circuit 30 is provided between the output side of the analog circuit 10 whose operation is controlled by a power-down signal PD and the input side of the logic circuit 20, and the latch circuit 30 is controlled by the power-down signal PD. In the state where the power-down signal PD is set in the "H" state and the analog circuit 10 is set in the operation state, and a signal S10 of a desired level is output, the power-down signal PD is switched into the "L" state. Accordingly, the operation of the analog circuit 10 is stopped and the signal S10 is set always in the "H" state. The signal S10 of the analog circuit 10 just before the power-down signal PD is switched into the "L" state is held in the latch circuit 30, and imparted to the logic circuit 20 as a signal S30. COPYRIGHT: (C)2007,JPO&INPIT</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS SEMICONDUCTOR DEVICES TESTING |
| title | SEMICONDUCTOR INTEGRATED CIRCUIT AND ITS TEST METHOD |
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