TESTING DEVICE AND TESTING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT
PROBLEM TO BE SOLVED: To enable test of a tested circuit such as a memory or an analog circuit that cannot be scanned, an input/output circuit, and a signal line between the input/output circuit and tested circuit. SOLUTION: A test device 1 of a semiconductor integrated circuit comprises the input/o...
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| creator | KAMATA TETSUO |
| description | PROBLEM TO BE SOLVED: To enable test of a tested circuit such as a memory or an analog circuit that cannot be scanned, an input/output circuit, and a signal line between the input/output circuit and tested circuit. SOLUTION: A test device 1 of a semiconductor integrated circuit comprises the input/output circuit 2, the tested circuit 3 formed of a SRAM, a logic circuit 4, a test circuit 5, a multiplexer MUX1, and a multiplexer MUX2. The test device 1 has a feedback loop where a signal of a node N13 on the output side of the multiplexer MUX1 is inputted into a test signal generating section 6 of the test circuit 5, and is inputted to one of the input sides of the multiplexer MUX1 via a test signal generating section 6. The test device 1 also has a feedback loop where a signal of a node N21 on the output side of the multiplexer MUX2 is inputted into a determination circuit section 7 of the test circuit 5, and is inputted to one of the input sides of the multiplexer MUX2 via the determination circuit section 7. COPYRIGHT: (C)2006,JPO&NCIPI |
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SOLUTION: A test device 1 of a semiconductor integrated circuit comprises the input/output circuit 2, the tested circuit 3 formed of a SRAM, a logic circuit 4, a test circuit 5, a multiplexer MUX1, and a multiplexer MUX2. The test device 1 has a feedback loop where a signal of a node N13 on the output side of the multiplexer MUX1 is inputted into a test signal generating section 6 of the test circuit 5, and is inputted to one of the input sides of the multiplexer MUX1 via a test signal generating section 6. The test device 1 also has a feedback loop where a signal of a node N21 on the output side of the multiplexer MUX2 is inputted into a determination circuit section 7 of the test circuit 5, and is inputted to one of the input sides of the multiplexer MUX2 via the determination circuit section 7. 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| subjects | MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS TESTING |
| title | TESTING DEVICE AND TESTING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT |
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