METHOD OF RELIABILITY SIMULATION OF SEMICONDUCTOR DEVICE, AND RELIABILITY SIMULATOR

PROBLEM TO BE SOLVED: To realize NBTI deterioration simulation and TDDB failure simulation which are very accurate and have wide application by creating an accurate NBTI (Negative Bias Temperature Instability) life model and TDDB (Time Dependent Dielectric Breakdown) life model and using them. SOLUT...

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description PROBLEM TO BE SOLVED: To realize NBTI deterioration simulation and TDDB failure simulation which are very accurate and have wide application by creating an accurate NBTI (Negative Bias Temperature Instability) life model and TDDB (Time Dependent Dielectric Breakdown) life model and using them. SOLUTION: When performing the reliability simulation of a semiconductor device based on the estimated value of the NBTI deterioration of a MOS transistor constituting the semiconductor device, a parameter Age which indicates an amount of accumulated NBTI stress with respect to the MOS transistor is calculated by a model expression expressed by Age=C ∫[(Ih/Area)m]dt, where Ih is a hole current in the gate insulation film of the MOS transistor, Area is a gate area of the MOS transistor, t is NBTI stress time, m is a model parameter, and C is a proportional constant. COPYRIGHT: (C)2006,JPO&NCIPI
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2006140284A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2006140284A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2006140284A3</originalsourceid><addsrcrecordid>eNrjZAj2dQ3x8HdR8HdTCHL18XR08vTxDIlUCPb0DfVxDPH09wPJBLv6ejr7-7mEOof4Bym4uIZ5OrvqKDj6uWDT4x_Ew8CalphTnMoLpbkZlNxcQ5w9dFML8uNTiwsSk1PzUkvivQKMDAzMDE0MjCxMHI2JUgQAclgwdg</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>METHOD OF RELIABILITY SIMULATION OF SEMICONDUCTOR DEVICE, AND RELIABILITY SIMULATOR</title><source>esp@cenet</source><creator>KOIKE NORIO</creator><creatorcontrib>KOIKE NORIO</creatorcontrib><description>PROBLEM TO BE SOLVED: To realize NBTI deterioration simulation and TDDB failure simulation which are very accurate and have wide application by creating an accurate NBTI (Negative Bias Temperature Instability) life model and TDDB (Time Dependent Dielectric Breakdown) life model and using them. SOLUTION: When performing the reliability simulation of a semiconductor device based on the estimated value of the NBTI deterioration of a MOS transistor constituting the semiconductor device, a parameter Age which indicates an amount of accumulated NBTI stress with respect to the MOS transistor is calculated by a model expression expressed by Age=C ∫[(Ih/Area)m]dt, where Ih is a hole current in the gate insulation film of the MOS transistor, Area is a gate area of the MOS transistor, t is NBTI stress time, m is a model parameter, and C is a proportional constant. COPYRIGHT: (C)2006,JPO&amp;NCIPI</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; PHYSICS ; SEMICONDUCTOR DEVICES</subject><creationdate>2006</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20060601&amp;DB=EPODOC&amp;CC=JP&amp;NR=2006140284A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20060601&amp;DB=EPODOC&amp;CC=JP&amp;NR=2006140284A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KOIKE NORIO</creatorcontrib><title>METHOD OF RELIABILITY SIMULATION OF SEMICONDUCTOR DEVICE, AND RELIABILITY SIMULATOR</title><description>PROBLEM TO BE SOLVED: To realize NBTI deterioration simulation and TDDB failure simulation which are very accurate and have wide application by creating an accurate NBTI (Negative Bias Temperature Instability) life model and TDDB (Time Dependent Dielectric Breakdown) life model and using them. SOLUTION: When performing the reliability simulation of a semiconductor device based on the estimated value of the NBTI deterioration of a MOS transistor constituting the semiconductor device, a parameter Age which indicates an amount of accumulated NBTI stress with respect to the MOS transistor is calculated by a model expression expressed by Age=C ∫[(Ih/Area)m]dt, where Ih is a hole current in the gate insulation film of the MOS transistor, Area is a gate area of the MOS transistor, t is NBTI stress time, m is a model parameter, and C is a proportional constant. COPYRIGHT: (C)2006,JPO&amp;NCIPI</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2006</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZAj2dQ3x8HdR8HdTCHL18XR08vTxDIlUCPb0DfVxDPH09wPJBLv6ejr7-7mEOof4Bym4uIZ5OrvqKDj6uWDT4x_Ew8CalphTnMoLpbkZlNxcQ5w9dFML8uNTiwsSk1PzUkvivQKMDAzMDE0MjCxMHI2JUgQAclgwdg</recordid><startdate>20060601</startdate><enddate>20060601</enddate><creator>KOIKE NORIO</creator><scope>EVB</scope></search><sort><creationdate>20060601</creationdate><title>METHOD OF RELIABILITY SIMULATION OF SEMICONDUCTOR DEVICE, AND RELIABILITY SIMULATOR</title><author>KOIKE NORIO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2006140284A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2006</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>KOIKE NORIO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KOIKE NORIO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>METHOD OF RELIABILITY SIMULATION OF SEMICONDUCTOR DEVICE, AND RELIABILITY SIMULATOR</title><date>2006-06-01</date><risdate>2006</risdate><abstract>PROBLEM TO BE SOLVED: To realize NBTI deterioration simulation and TDDB failure simulation which are very accurate and have wide application by creating an accurate NBTI (Negative Bias Temperature Instability) life model and TDDB (Time Dependent Dielectric Breakdown) life model and using them. SOLUTION: When performing the reliability simulation of a semiconductor device based on the estimated value of the NBTI deterioration of a MOS transistor constituting the semiconductor device, a parameter Age which indicates an amount of accumulated NBTI stress with respect to the MOS transistor is calculated by a model expression expressed by Age=C ∫[(Ih/Area)m]dt, where Ih is a hole current in the gate insulation film of the MOS transistor, Area is a gate area of the MOS transistor, t is NBTI stress time, m is a model parameter, and C is a proportional constant. COPYRIGHT: (C)2006,JPO&amp;NCIPI</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
PHYSICS
SEMICONDUCTOR DEVICES
title METHOD OF RELIABILITY SIMULATION OF SEMICONDUCTOR DEVICE, AND RELIABILITY SIMULATOR
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-23T05%3A18%3A10IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=KOIKE%20NORIO&rft.date=2006-06-01&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJP2006140284A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true