SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR

PROBLEM TO BE SOLVED: To provide a semiconductor device in which a circuit element showing resistance to high voltage and suppressed characteristic fluctuation is formed on the surface of an SOI (silicon on insulator) board and which can be manufactured inexpensively, and to provide a manufacturing...

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Hauptverfasser: KUZUHARA TAKESHI, YAMADA AKIRA
Format: Patent
Sprache:eng
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BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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creator KUZUHARA TAKESHI
YAMADA AKIRA
description PROBLEM TO BE SOLVED: To provide a semiconductor device in which a circuit element showing resistance to high voltage and suppressed characteristic fluctuation is formed on the surface of an SOI (silicon on insulator) board and which can be manufactured inexpensively, and to provide a manufacturing method for the semiconductor device. SOLUTION: In the semiconductor device 100, the circuit element having a p-type conductive diffusion region 6 and n-type conductive diffusion regions 7, 7a is formed on the surface of a first semiconductor layer 1 on the main surface side of the SOI structure semiconductor board 12 having a buried oxide film 3. A trench 5 with a side groove 5m made by expanding the width of the trench along the buried oxide film 3 is formed on the semiconductor device 100 to extend from the surface of the first semiconductor layer 1 to reach the buried oxide film 3. At least either of the p-type conductive diffusion region 6 and the n-type conductive diffusion regions 7, 7a is located above the side groove 5m. COPYRIGHT: (C)2006,JPO&NCIPI
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2006100544A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2006100544A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2006100544A3</originalsourceid><addsrcrecordid>eNrjZDALdvX1dPb3cwl1DvEPUnBxDfN0dlVw9HNR8HX0C3VzdA4JDfL0c1fwdQ3x8HdRCPFwDXJ18w_iYWBNS8wpTuWF0twMSm6uIc4euqkF-fGpxQWJyal5qSXxXgFGBgZmhgYGpiYmjsZEKQIAdTcocw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR</title><source>esp@cenet</source><creator>KUZUHARA TAKESHI ; YAMADA AKIRA</creator><creatorcontrib>KUZUHARA TAKESHI ; YAMADA AKIRA</creatorcontrib><description>PROBLEM TO BE SOLVED: To provide a semiconductor device in which a circuit element showing resistance to high voltage and suppressed characteristic fluctuation is formed on the surface of an SOI (silicon on insulator) board and which can be manufactured inexpensively, and to provide a manufacturing method for the semiconductor device. SOLUTION: In the semiconductor device 100, the circuit element having a p-type conductive diffusion region 6 and n-type conductive diffusion regions 7, 7a is formed on the surface of a first semiconductor layer 1 on the main surface side of the SOI structure semiconductor board 12 having a buried oxide film 3. A trench 5 with a side groove 5m made by expanding the width of the trench along the buried oxide film 3 is formed on the semiconductor device 100 to extend from the surface of the first semiconductor layer 1 to reach the buried oxide film 3. At least either of the p-type conductive diffusion region 6 and the n-type conductive diffusion regions 7, 7a is located above the side groove 5m. COPYRIGHT: (C)2006,JPO&amp;NCIPI</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2006</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20060413&amp;DB=EPODOC&amp;CC=JP&amp;NR=2006100544A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76516</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20060413&amp;DB=EPODOC&amp;CC=JP&amp;NR=2006100544A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KUZUHARA TAKESHI</creatorcontrib><creatorcontrib>YAMADA AKIRA</creatorcontrib><title>SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR</title><description>PROBLEM TO BE SOLVED: To provide a semiconductor device in which a circuit element showing resistance to high voltage and suppressed characteristic fluctuation is formed on the surface of an SOI (silicon on insulator) board and which can be manufactured inexpensively, and to provide a manufacturing method for the semiconductor device. SOLUTION: In the semiconductor device 100, the circuit element having a p-type conductive diffusion region 6 and n-type conductive diffusion regions 7, 7a is formed on the surface of a first semiconductor layer 1 on the main surface side of the SOI structure semiconductor board 12 having a buried oxide film 3. A trench 5 with a side groove 5m made by expanding the width of the trench along the buried oxide film 3 is formed on the semiconductor device 100 to extend from the surface of the first semiconductor layer 1 to reach the buried oxide film 3. At least either of the p-type conductive diffusion region 6 and the n-type conductive diffusion regions 7, 7a is located above the side groove 5m. COPYRIGHT: (C)2006,JPO&amp;NCIPI</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2006</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDALdvX1dPb3cwl1DvEPUnBxDfN0dlVw9HNR8HX0C3VzdA4JDfL0c1fwdQ3x8HdRCPFwDXJ18w_iYWBNS8wpTuWF0twMSm6uIc4euqkF-fGpxQWJyal5qSXxXgFGBgZmhgYGpiYmjsZEKQIAdTcocw</recordid><startdate>20060413</startdate><enddate>20060413</enddate><creator>KUZUHARA TAKESHI</creator><creator>YAMADA AKIRA</creator><scope>EVB</scope></search><sort><creationdate>20060413</creationdate><title>SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR</title><author>KUZUHARA TAKESHI ; YAMADA AKIRA</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2006100544A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2006</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>KUZUHARA TAKESHI</creatorcontrib><creatorcontrib>YAMADA AKIRA</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KUZUHARA TAKESHI</au><au>YAMADA AKIRA</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR</title><date>2006-04-13</date><risdate>2006</risdate><abstract>PROBLEM TO BE SOLVED: To provide a semiconductor device in which a circuit element showing resistance to high voltage and suppressed characteristic fluctuation is formed on the surface of an SOI (silicon on insulator) board and which can be manufactured inexpensively, and to provide a manufacturing method for the semiconductor device. SOLUTION: In the semiconductor device 100, the circuit element having a p-type conductive diffusion region 6 and n-type conductive diffusion regions 7, 7a is formed on the surface of a first semiconductor layer 1 on the main surface side of the SOI structure semiconductor board 12 having a buried oxide film 3. A trench 5 with a side groove 5m made by expanding the width of the trench along the buried oxide film 3 is formed on the semiconductor device 100 to extend from the surface of the first semiconductor layer 1 to reach the buried oxide film 3. At least either of the p-type conductive diffusion region 6 and the n-type conductive diffusion regions 7, 7a is located above the side groove 5m. COPYRIGHT: (C)2006,JPO&amp;NCIPI</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-14T06%3A47%3A26IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=KUZUHARA%20TAKESHI&rft.date=2006-04-13&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJP2006100544A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true