DATA PROCESSOR, DELAY CIRCUIT AND DELAY ELEMENT

PROBLEM TO BE SOLVED: To secure the margin of a data output timing to an SDRAM against the fluctuation of a process or the change of an operation environment. SOLUTION: An SDRAM interface controller is provided with a data output circuit (30) and an output control circuit (31) for controlling the output timing of the data output circuit synchronously with a memory clock signal (CLK) to an SDRAM, and the output control circuit is provided with a variable delay circuit (40) and a DLL circuit (41). Based on a phase difference between a memory clock signal and a delay clock signal obtained by delaying the memory clock signal by an internal delay circuit, the DLL circuit generates delay control data (42) to delay the delay clock signal by a predetermined phase to the memory clock signal, and the variable delay circuit specifies the output timing of the data output circuit by delaying the memory clock signal by the delay control data. The SDRAM interface controller updates the delay control data to the variable delay circuit synchronously with the refresh operation of the SDRAM. COPYRIGHT: (C)2006,JPO&NCIPI