COMPUTER SYSTEM
PROBLEM TO BE SOLVED: To execute a plurality of instructions out of order like parallel processing by avoiding the occurrence of a data error due to dependability. SOLUTION: A computer system is disclosed which is composed of an execution unit including an instruction fetch unit and a load store uni...
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| creator | WANG JOHANNES SENTER CHERYL |
| description | PROBLEM TO BE SOLVED: To execute a plurality of instructions out of order like parallel processing by avoiding the occurrence of a data error due to dependability. SOLUTION: A computer system is disclosed which is composed of an execution unit including an instruction fetch unit and a load store unit 205 adapted to perform a load request to a memory system out of order regarding all of instructions in an instruction window and to perform a store request in order regarding all of the instructions in the instruction window, wherein the load store unit 205 includes an address collision means to perform the load request when no address collisions and no write pendings are detected, an address path 220 adapted to manage a plurality of addresses and a data path 210 constituted so that data returned from a memory system is aligned and returned. COPYRIGHT: (C)2005,JPO&NCIPI |
| format | Patent |
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SOLUTION: A computer system is disclosed which is composed of an execution unit including an instruction fetch unit and a load store unit 205 adapted to perform a load request to a memory system out of order regarding all of instructions in an instruction window and to perform a store request in order regarding all of the instructions in the instruction window, wherein the load store unit 205 includes an address collision means to perform the load request when no address collisions and no write pendings are detected, an address path 220 adapted to manage a plurality of addresses and a data path 210 constituted so that data returned from a memory system is aligned and returned. COPYRIGHT: (C)2005,JPO&NCIPI</description><edition>7</edition><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2005</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20050623&DB=EPODOC&CC=JP&NR=2005166046A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20050623&DB=EPODOC&CC=JP&NR=2005166046A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>WANG JOHANNES</creatorcontrib><creatorcontrib>SENTER CHERYL</creatorcontrib><title>COMPUTER SYSTEM</title><description>PROBLEM TO BE SOLVED: To execute a plurality of instructions out of order like parallel processing by avoiding the occurrence of a data error due to dependability. SOLUTION: A computer system is disclosed which is composed of an execution unit including an instruction fetch unit and a load store unit 205 adapted to perform a load request to a memory system out of order regarding all of instructions in an instruction window and to perform a store request in order regarding all of the instructions in the instruction window, wherein the load store unit 205 includes an address collision means to perform the load request when no address collisions and no write pendings are detected, an address path 220 adapted to manage a plurality of addresses and a data path 210 constituted so that data returned from a memory system is aligned and returned. COPYRIGHT: (C)2005,JPO&NCIPI</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2005</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZOB39vcNCA1xDVIIjgwOcfXlYWBNS8wpTuWF0twMSm6uIc4euqkF-fGpxQWJyal5qSXxXgFGBgamhmZmBiZmjsZEKQIAMngd2g</recordid><startdate>20050623</startdate><enddate>20050623</enddate><creator>WANG JOHANNES</creator><creator>SENTER CHERYL</creator><scope>EVB</scope></search><sort><creationdate>20050623</creationdate><title>COMPUTER SYSTEM</title><author>WANG JOHANNES ; SENTER CHERYL</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2005166046A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2005</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>WANG JOHANNES</creatorcontrib><creatorcontrib>SENTER CHERYL</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>WANG JOHANNES</au><au>SENTER CHERYL</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>COMPUTER SYSTEM</title><date>2005-06-23</date><risdate>2005</risdate><abstract>PROBLEM TO BE SOLVED: To execute a plurality of instructions out of order like parallel processing by avoiding the occurrence of a data error due to dependability. SOLUTION: A computer system is disclosed which is composed of an execution unit including an instruction fetch unit and a load store unit 205 adapted to perform a load request to a memory system out of order regarding all of instructions in an instruction window and to perform a store request in order regarding all of the instructions in the instruction window, wherein the load store unit 205 includes an address collision means to perform the load request when no address collisions and no write pendings are detected, an address path 220 adapted to manage a plurality of addresses and a data path 210 constituted so that data returned from a memory system is aligned and returned. COPYRIGHT: (C)2005,JPO&NCIPI</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
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| language | eng |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | COMPUTER SYSTEM |
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