MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device which is conformable to prevent a bit line hard mask from damaging in the case of storage node contact etching. SOLUTION: The manufacturing method comprises steps of: forming a primary interlayer insulating film on a s...
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creator | KIN TOSHAKU HWANG CHANG-YOUN JUNG JIN-KI |
description | PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device which is conformable to prevent a bit line hard mask from damaging in the case of storage node contact etching. SOLUTION: The manufacturing method comprises steps of: forming a primary interlayer insulating film on a substrate; forming a plurality of bit line patterns by successively laminating wiring films and hard masks on the primary interlayer insulating film; forming a primary barrier layer on the primary interlayer insulating film; forming a secondary interlayer insulating film on the primary barrier layer by filling a gap between the bit line patterns; partially remaining the secondary interlayer insulating film between the bit line patterns; forming a secondary barrier layer having a step coverage of such a form that a first thickness covering an upper stage and a corner of the bit line pattern is thicker than a second thickness covering the side face of the pattern on the remaining secondary interlayer insulating film and the primary barrier layer; forming a contact hole exposing a plug surface by etching back the secondary barrier layer; and forming a spacer of the secondary interlayer insulating film at the side face of the bit line pattern. COPYRIGHT: (C)2005,JPO&NCIPI |
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SOLUTION: The manufacturing method comprises steps of: forming a primary interlayer insulating film on a substrate; forming a plurality of bit line patterns by successively laminating wiring films and hard masks on the primary interlayer insulating film; forming a primary barrier layer on the primary interlayer insulating film; forming a secondary interlayer insulating film on the primary barrier layer by filling a gap between the bit line patterns; partially remaining the secondary interlayer insulating film between the bit line patterns; forming a secondary barrier layer having a step coverage of such a form that a first thickness covering an upper stage and a corner of the bit line pattern is thicker than a second thickness covering the side face of the pattern on the remaining secondary interlayer insulating film and the primary barrier layer; forming a contact hole exposing a plug surface by etching back the secondary barrier layer; and forming a spacer of the secondary interlayer insulating film at the side face of the bit line pattern. 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SOLUTION: The manufacturing method comprises steps of: forming a primary interlayer insulating film on a substrate; forming a plurality of bit line patterns by successively laminating wiring films and hard masks on the primary interlayer insulating film; forming a primary barrier layer on the primary interlayer insulating film; forming a secondary interlayer insulating film on the primary barrier layer by filling a gap between the bit line patterns; partially remaining the secondary interlayer insulating film between the bit line patterns; forming a secondary barrier layer having a step coverage of such a form that a first thickness covering an upper stage and a corner of the bit line pattern is thicker than a second thickness covering the side face of the pattern on the remaining secondary interlayer insulating film and the primary barrier layer; forming a contact hole exposing a plug surface by etching back the secondary barrier layer; and forming a spacer of the secondary interlayer insulating film at the side face of the bit line pattern. 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SOLUTION: The manufacturing method comprises steps of: forming a primary interlayer insulating film on a substrate; forming a plurality of bit line patterns by successively laminating wiring films and hard masks on the primary interlayer insulating film; forming a primary barrier layer on the primary interlayer insulating film; forming a secondary interlayer insulating film on the primary barrier layer by filling a gap between the bit line patterns; partially remaining the secondary interlayer insulating film between the bit line patterns; forming a secondary barrier layer having a step coverage of such a form that a first thickness covering an upper stage and a corner of the bit line pattern is thicker than a second thickness covering the side face of the pattern on the remaining secondary interlayer insulating film and the primary barrier layer; forming a contact hole exposing a plug surface by etching back the secondary barrier layer; and forming a spacer of the secondary interlayer insulating film at the side face of the bit line pattern. COPYRIGHT: (C)2005,JPO&NCIPI</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE |
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