ETCHING METHOD

PROBLEM TO BE SOLVED: To provide an etching method which can easily form a mesa shape in a lamination body composed of a plurality of semiconductor layers, and can prevent disconnection of an electrode arranged so as to cover the mesa, and moreover, enables superior shape controllability. SOLUTION:...

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1. Verfasser:	SAGA NORIHIRO
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Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS DEVICES USING STIMULATED EMISSION ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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creator	SAGA NORIHIRO
description	PROBLEM TO BE SOLVED: To provide an etching method which can easily form a mesa shape in a lamination body composed of a plurality of semiconductor layers, and can prevent disconnection of an electrode arranged so as to cover the mesa, and moreover, enables superior shape controllability. SOLUTION: This etching method includes the steps of preparing a substrate 1a wherein both sides of a striping mesa including an MQW-SCH layer 24 arranged on a semiconductor substrate 90a are buried with InP layers 32a, 34a, and an InP layer 28a and a GaInAs layer 30a are formed thereon; forming an insulator mask M1 on the GaInAs layer 30a in stripes and dry-etching the GaInAs layer 30a; and continuously dry-etching the InP layers 28a, 32a and 34a. The bias voltage in the etching process of the GaInAs layer 30a is reduced as compared with that in the etching process of the InP layers 28a, 32a and 34a, and the ICP output in the former is increased as compared with that in the latter. COPYRIGHT: (C)2004,JPO&NCIPI
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SOLUTION: This etching method includes the steps of preparing a substrate 1a wherein both sides of a striping mesa including an MQW-SCH layer 24 arranged on a semiconductor substrate 90a are buried with InP layers 32a, 34a, and an InP layer 28a and a GaInAs layer 30a are formed thereon; forming an insulator mask M1 on the GaInAs layer 30a in stripes and dry-etching the GaInAs layer 30a; and continuously dry-etching the InP layers 28a, 32a and 34a. The bias voltage in the etching process of the GaInAs layer 30a is reduced as compared with that in the etching process of the InP layers 28a, 32a and 34a, and the ICP output in the former is increased as compared with that in the latter. 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SOLUTION: This etching method includes the steps of preparing a substrate 1a wherein both sides of a striping mesa including an MQW-SCH layer 24 arranged on a semiconductor substrate 90a are buried with InP layers 32a, 34a, and an InP layer 28a and a GaInAs layer 30a are formed thereon; forming an insulator mask M1 on the GaInAs layer 30a in stripes and dry-etching the GaInAs layer 30a; and continuously dry-etching the InP layers 28a, 32a and 34a. The bias voltage in the etching process of the GaInAs layer 30a is reduced as compared with that in the etching process of the InP layers 28a, 32a and 34a, and the ICP output in the former is increased as compared with that in the latter. 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subjects	BASIC ELECTRIC ELEMENTS DEVICES USING STIMULATED EMISSION ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
title	ETCHING METHOD
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