METHOD FOR TESTING A PLURALITY OF MIXED LOADED MEMORY SITE LOCATED ON COMPUTER CHIP AND INTEGRATED CIRCUIT

PROBLEM TO BE SOLVED: To provide a method and a device, capable of testing a multiple memory array regarding multiplex processor cores (105-108) on a single computer chip (100). SOLUTION: A map is generated, which shows the locations where memory faults have occurred in the memory mixed loaded array...

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Bibliographische Detailangaben

Hauptverfasser:	JARBOE JR JAMES M, HO VAN T, WRIGHT NATHAN W, SCHUTT NICHOLAS H
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY INFORMATION STORAGE MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS SEMICONDUCTOR DEVICES STATIC STORES TESTING
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