METHOD FOR TESTING A PLURALITY OF MIXED LOADED MEMORY SITE LOCATED ON COMPUTER CHIP AND INTEGRATED CIRCUIT
PROBLEM TO BE SOLVED: To provide a method and a device, capable of testing a multiple memory array regarding multiplex processor cores (105-108) on a single computer chip (100). SOLUTION: A map is generated, which shows the locations where memory faults have occurred in the memory mixed loaded array...
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| creator | JARBOE JR JAMES M HO VAN T WRIGHT NATHAN W SCHUTT NICHOLAS H |
| description | PROBLEM TO BE SOLVED: To provide a method and a device, capable of testing a multiple memory array regarding multiplex processor cores (105-108) on a single computer chip (100). SOLUTION: A map is generated, which shows the locations where memory faults have occurred in the memory mixed loaded arrays (110-113). When a test process decided that the mixed memory array cannot be or can be mended, a signal showing that it is incapable or capable of being mended respectively is output directly to an external testing device. When a fault is not found, a signal showing that the mixed memory array contains no fault is given to the external testing device. Based on these status signals, the external testing device can decide whether the data are set to be loaded on each mixed memory, or to be disregarded, thereby enabling the outer testing device to reduce the testing time for the memory of the device. COPYRIGHT: (C)2004,JPO&NCIPI |
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| subjects | BASIC ELECTRIC ELEMENTS CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY INFORMATION STORAGE MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS SEMICONDUCTOR DEVICES STATIC STORES TESTING |
| title | METHOD FOR TESTING A PLURALITY OF MIXED LOADED MEMORY SITE LOCATED ON COMPUTER CHIP AND INTEGRATED CIRCUIT |
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