DUAL-GATE FIELD-EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREFOR

PROBLEM TO BE SOLVED: To provide a dual gate field-effect transistor (DGFET) structure, with a significantly reduced parasitic capacity in the source/drain region and its formation method. SOLUTION: This dual-gate field-effect transistor reduces the parasitic capacity in the DGFET structure by being...

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Hauptverfasser:	KEVIN K CHAN, HANAFI HUSSEIN I, SOLOMON PAUL M
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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creator	KEVIN K CHAN HANAFI HUSSEIN I SOLOMON PAUL M
description	PROBLEM TO BE SOLVED: To provide a dual gate field-effect transistor (DGFET) structure, with a significantly reduced parasitic capacity in the source/drain region and its formation method. SOLUTION: This dual-gate field-effect transistor reduces the parasitic capacity in the DGFET structure by being provided with a self-aligned isolation region 44. Furthermore, the parasitic capacity of the structure is further reduced, by enabling substantial oxidization to occur at a back gate, which is made possible by coating a silicon contained channel 18. COPYRIGHT: (C)2004,JPO&NCIPI
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title	DUAL-GATE FIELD-EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREFOR
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