SCANNING TEST CIRCUIT AND TEST METHOD

SCANNING TEST CIRCUIT AND TEST METHOD

PROBLEM TO BE SOLVED: To divide scanning chains into a plurality of portions to allow test frequencies in the divided scanning chains more than those in the undivided ones. SOLUTION: This scanning test circuit is provided with the plurality of scanning chains 11-13 comprising a plurality of scanning...

Ausführliche Beschreibung

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Bibliographische Detailangaben
1. Verfasser: IMANISHI TAKANORI
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
SEMICONDUCTOR DEVICES
TESTING
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Beschreibung
Zusammenfassung:PROBLEM TO BE SOLVED: To divide scanning chains into a plurality of portions to allow test frequencies in the divided scanning chains more than those in the undivided ones. SOLUTION: This scanning test circuit is provided with the plurality of scanning chains 11-13 comprising a plurality of scanning flip-flops 1 and a plurality of scanning flip-flops 3 with an input selector, spare input terminals 41, 42 for inputting test patterns into the scanning flip-flops 3 with the input selector, spare scanning output terminals 71, 72 for outputting the test patterns from the scanning flip-flops 1 in a preceding stage of the scanning flip-flops 3 with the input selector, and a mode setting circuit 81 for setting the scanning chain to be divided out of the scanning chains 11-13. COPYRIGHT: (C)2004,JPO&NCIPI