CIRCUIT FOR SELECTIVELY GENERATING AN OUTPUT SIGNAL FROM ONE OR MORE CLOCK SIGNALS

PROBLEM TO BE SOLVED: To provide a circuit (100) with which one of a plurality of input clock signals (CLK- SRC1,..., CLK- SRC- n) can be selected and passed on to an output signal (CLK- OUT). SOLUTION: The input clock signals are present at a multiplexer (MUX) which applies one of these signals depending on the selection signal (CFG- i) from its control input to its output. The output signal (MUX- OUT) of the multiplexer is supplied via a switch (S) and a signal latch (LATCH) to the output of the circuit as output signal (CLK- OUT). Switching between two input signals is controlled by a state machine (FSM) which first intransparently switches the signals latch (LATCH) after a change of the external configuration signal (CFG).