BANK CONTROL CIRCUIT OF RAM BUS DRAM AND SEMICONDUCTOR MEMORY UTILIZING THIS CIRCUIT

PROBLEM TO BE SOLVED: To provide a bank control circuit if a RAM bus DRAM in which circuit area can be reduced by sharing one bank per two bank in a control circuit controlling respective memory bank and an address latch circuit. SOLUTION: A semiconductor memory element performing dependent bank operation is provided with a plurality of banks 130 comprising memory cells, and a plurality of address latch circuits 170 which is shared by two banks being adjacent respectively out of a plurality of banks, receiving a global address signal, and latching a local address signal of a selected bank.