SEMICONDUCTOR INTEGRATED CIRCUIT
PROBLEM TO BE SOLVED: To reduce a standby current of a semiconductor integrated circuit operated synchronizing with a clock signal. SOLUTION: A control circuit receives a plurality of control signal synchronizing with a clock signal, and generates a timing signal in accordance with combination of th...
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creator | YAGISHITA YOSHIMASA |
description | PROBLEM TO BE SOLVED: To reduce a standby current of a semiconductor integrated circuit operated synchronizing with a clock signal. SOLUTION: A control circuit receives a plurality of control signal synchronizing with a clock signal, and generates a timing signal in accordance with combination of these control signals. A delay circuit delays an input signal received with asynchronism with a clock signal by the prescribed time. A receiving circuit receives an input signal delayed by the delay circuit synchronizing with no clock signal but a timing signal. That is, The receiving circuit is operated with asynchronism with a clock signal, receives only an input signal required for a semiconductor integrated circuit. Thereby, frequency of operation of the receiving circuit is reduced, power consumption can be reduced. As the number of circuits operated synchronizing with a clock signal can be decreased, a standby current can be reduced. Even if a frequency of a clock signal is increased, increment of a standby current is gentle. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2002304887A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2002304887A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2002304887A3</originalsourceid><addsrcrecordid>eNrjZFAIdvX1dPb3cwl1DvEPUvD0C3F1D3IMcXVRcPYMcg71DOFhYE1LzClO5YXS3AxKbq4hzh66qQX58anFBYnJqXmpJfFeAUYGBkbGBiYWFuaOxkQpAgBSpCKY</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SEMICONDUCTOR INTEGRATED CIRCUIT</title><source>esp@cenet</source><creator>YAGISHITA YOSHIMASA</creator><creatorcontrib>YAGISHITA YOSHIMASA</creatorcontrib><description>PROBLEM TO BE SOLVED: To reduce a standby current of a semiconductor integrated circuit operated synchronizing with a clock signal. SOLUTION: A control circuit receives a plurality of control signal synchronizing with a clock signal, and generates a timing signal in accordance with combination of these control signals. A delay circuit delays an input signal received with asynchronism with a clock signal by the prescribed time. A receiving circuit receives an input signal delayed by the delay circuit synchronizing with no clock signal but a timing signal. That is, The receiving circuit is operated with asynchronism with a clock signal, receives only an input signal required for a semiconductor integrated circuit. Thereby, frequency of operation of the receiving circuit is reduced, power consumption can be reduced. As the number of circuits operated synchronizing with a clock signal can be decreased, a standby current can be reduced. Even if a frequency of a clock signal is increased, increment of a standby current is gentle.</description><edition>7</edition><language>eng</language><subject>BASIC ELECTRONIC CIRCUITRY ; ELECTRICITY ; INFORMATION STORAGE ; PHYSICS ; PULSE TECHNIQUE ; STATIC STORES</subject><creationdate>2002</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20021018&DB=EPODOC&CC=JP&NR=2002304887A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20021018&DB=EPODOC&CC=JP&NR=2002304887A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>YAGISHITA YOSHIMASA</creatorcontrib><title>SEMICONDUCTOR INTEGRATED CIRCUIT</title><description>PROBLEM TO BE SOLVED: To reduce a standby current of a semiconductor integrated circuit operated synchronizing with a clock signal. SOLUTION: A control circuit receives a plurality of control signal synchronizing with a clock signal, and generates a timing signal in accordance with combination of these control signals. A delay circuit delays an input signal received with asynchronism with a clock signal by the prescribed time. A receiving circuit receives an input signal delayed by the delay circuit synchronizing with no clock signal but a timing signal. That is, The receiving circuit is operated with asynchronism with a clock signal, receives only an input signal required for a semiconductor integrated circuit. Thereby, frequency of operation of the receiving circuit is reduced, power consumption can be reduced. As the number of circuits operated synchronizing with a clock signal can be decreased, a standby current can be reduced. Even if a frequency of a clock signal is increased, increment of a standby current is gentle.</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRICITY</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>PULSE TECHNIQUE</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2002</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFAIdvX1dPb3cwl1DvEPUvD0C3F1D3IMcXVRcPYMcg71DOFhYE1LzClO5YXS3AxKbq4hzh66qQX58anFBYnJqXmpJfFeAUYGBkbGBiYWFuaOxkQpAgBSpCKY</recordid><startdate>20021018</startdate><enddate>20021018</enddate><creator>YAGISHITA YOSHIMASA</creator><scope>EVB</scope></search><sort><creationdate>20021018</creationdate><title>SEMICONDUCTOR INTEGRATED CIRCUIT</title><author>YAGISHITA YOSHIMASA</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2002304887A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2002</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>ELECTRICITY</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>PULSE TECHNIQUE</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>YAGISHITA YOSHIMASA</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>YAGISHITA YOSHIMASA</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR INTEGRATED CIRCUIT</title><date>2002-10-18</date><risdate>2002</risdate><abstract>PROBLEM TO BE SOLVED: To reduce a standby current of a semiconductor integrated circuit operated synchronizing with a clock signal. SOLUTION: A control circuit receives a plurality of control signal synchronizing with a clock signal, and generates a timing signal in accordance with combination of these control signals. A delay circuit delays an input signal received with asynchronism with a clock signal by the prescribed time. A receiving circuit receives an input signal delayed by the delay circuit synchronizing with no clock signal but a timing signal. That is, The receiving circuit is operated with asynchronism with a clock signal, receives only an input signal required for a semiconductor integrated circuit. Thereby, frequency of operation of the receiving circuit is reduced, power consumption can be reduced. As the number of circuits operated synchronizing with a clock signal can be decreased, a standby current can be reduced. Even if a frequency of a clock signal is increased, increment of a standby current is gentle.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRONIC CIRCUITRY ELECTRICITY INFORMATION STORAGE PHYSICS PULSE TECHNIQUE STATIC STORES |
title | SEMICONDUCTOR INTEGRATED CIRCUIT |
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