MOUNTING METHOD AT WAFER LEVEL
PROBLEM TO BE SOLVED: To provide a mounting method at wafer level for a simplified process by appropriately forming a stress buffer layer on a wafer instead of an underfill. SOLUTION: A patterned photoresist is formed on a wafer 100 so as to cover a bump formation position and a plurality of scribe...
Gespeichert in:
1. Verfasser: | |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | YIH MUH-MIN |
description | PROBLEM TO BE SOLVED: To provide a mounting method at wafer level for a simplified process by appropriately forming a stress buffer layer on a wafer instead of an underfill. SOLUTION: A patterned photoresist is formed on a wafer 100 so as to cover a bump formation position and a plurality of scribe lines. A stress buffer layer 109 is formed on a region not covered with the photoresist. After the photoresist is removed, a plurality of first openings are provided on the stress buffer layer 109. The stress buffer layer and the scribe line are covered with a stencil comprising a plurality of second openings 115 or a second patterned photoresist 114. The first opening is exposed at the second opening, which is filled with a solder material 116 for a reflow process. Then the stencil or the second patterned photoresist 114 is removed. A wafer packaged like this is directly connected to an external carrier after dicing. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2002299511A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2002299511A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2002299511A3</originalsourceid><addsrcrecordid>eNrjZJDz9Q_1C_H0c1fwdQ3x8HdRcAxRCHd0cw1S8HENc_XhYWBNS8wpTuWF0twMSm6uIc4euqkF-fGpxQWJyal5qSXxXgFGBgZGRpaWpoaGjsZEKQIA6vIhqw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>MOUNTING METHOD AT WAFER LEVEL</title><source>esp@cenet</source><creator>YIH MUH-MIN</creator><creatorcontrib>YIH MUH-MIN</creatorcontrib><description>PROBLEM TO BE SOLVED: To provide a mounting method at wafer level for a simplified process by appropriately forming a stress buffer layer on a wafer instead of an underfill. SOLUTION: A patterned photoresist is formed on a wafer 100 so as to cover a bump formation position and a plurality of scribe lines. A stress buffer layer 109 is formed on a region not covered with the photoresist. After the photoresist is removed, a plurality of first openings are provided on the stress buffer layer 109. The stress buffer layer and the scribe line are covered with a stencil comprising a plurality of second openings 115 or a second patterned photoresist 114. The first opening is exposed at the second opening, which is filled with a solder material 116 for a reflow process. Then the stencil or the second patterned photoresist 114 is removed. A wafer packaged like this is directly connected to an external carrier after dicing.</description><edition>7</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2002</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20021011&DB=EPODOC&CC=JP&NR=2002299511A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20021011&DB=EPODOC&CC=JP&NR=2002299511A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>YIH MUH-MIN</creatorcontrib><title>MOUNTING METHOD AT WAFER LEVEL</title><description>PROBLEM TO BE SOLVED: To provide a mounting method at wafer level for a simplified process by appropriately forming a stress buffer layer on a wafer instead of an underfill. SOLUTION: A patterned photoresist is formed on a wafer 100 so as to cover a bump formation position and a plurality of scribe lines. A stress buffer layer 109 is formed on a region not covered with the photoresist. After the photoresist is removed, a plurality of first openings are provided on the stress buffer layer 109. The stress buffer layer and the scribe line are covered with a stencil comprising a plurality of second openings 115 or a second patterned photoresist 114. The first opening is exposed at the second opening, which is filled with a solder material 116 for a reflow process. Then the stencil or the second patterned photoresist 114 is removed. A wafer packaged like this is directly connected to an external carrier after dicing.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2002</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJDz9Q_1C_H0c1fwdQ3x8HdRcAxRCHd0cw1S8HENc_XhYWBNS8wpTuWF0twMSm6uIc4euqkF-fGpxQWJyal5qSXxXgFGBgZGRpaWpoaGjsZEKQIA6vIhqw</recordid><startdate>20021011</startdate><enddate>20021011</enddate><creator>YIH MUH-MIN</creator><scope>EVB</scope></search><sort><creationdate>20021011</creationdate><title>MOUNTING METHOD AT WAFER LEVEL</title><author>YIH MUH-MIN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2002299511A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2002</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>YIH MUH-MIN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>YIH MUH-MIN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>MOUNTING METHOD AT WAFER LEVEL</title><date>2002-10-11</date><risdate>2002</risdate><abstract>PROBLEM TO BE SOLVED: To provide a mounting method at wafer level for a simplified process by appropriately forming a stress buffer layer on a wafer instead of an underfill. SOLUTION: A patterned photoresist is formed on a wafer 100 so as to cover a bump formation position and a plurality of scribe lines. A stress buffer layer 109 is formed on a region not covered with the photoresist. After the photoresist is removed, a plurality of first openings are provided on the stress buffer layer 109. The stress buffer layer and the scribe line are covered with a stencil comprising a plurality of second openings 115 or a second patterned photoresist 114. The first opening is exposed at the second opening, which is filled with a solder material 116 for a reflow process. Then the stencil or the second patterned photoresist 114 is removed. A wafer packaged like this is directly connected to an external carrier after dicing.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_epo_espacenet_JP2002299511A |
source | esp@cenet |
subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | MOUNTING METHOD AT WAFER LEVEL |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-02T17%3A51%3A54IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=YIH%20MUH-MIN&rft.date=2002-10-11&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJP2002299511A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |