SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURING METHOD
PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device which realizes reduction in a manufacturing cost by cutting the number of photomasks, and its manufacturing method. SOLUTION: An SIMOX substrate is used, wherein an oxide film 8 is formed in a substrate 9 and an n- layer 2 is...
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creator | MATSUZAKI KAZUO |
description | PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device which realizes reduction in a manufacturing cost by cutting the number of photomasks, and its manufacturing method. SOLUTION: An SIMOX substrate is used, wherein an oxide film 8 is formed in a substrate 9 and an n- layer 2 is formed thereon. In the n- layer 2, an n-channel MOSFET (NMOS) and a p-channel MOSFET (PMOS) of a CMOS cell 1 are formed isolated and independent via an isolation groove, respectively. A p-well region 3 and an n+ source region 4 are formed to self-align using a gate electrode 12 as a mask. By using the isolation groove, it is possible to eliminate the need for an LOCOS oxide film and a stopper region, and to greatly cut the number of photomasks necessary in a manufacturing process by the application of the isolation groove formation and self alignment. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2002170957A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2002170957A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2002170957A3</originalsourceid><addsrcrecordid>eNqNyrEKwjAQANAsDqL-w-EuxIqUjuHu2p6QRNKLaykSJ9FC_X9c_ACnt7y1oYG9YAyUUWMCCcpdcsoEKAmzKBDfBBlcIBAdwLuQW4eak4QOPGsfaWtWj-m5lN3Pjdm3rNgfyvweyzJP9_Iqn_FyraytjrVtzrU7_ZW-yKEsYg</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURING METHOD</title><source>esp@cenet</source><creator>MATSUZAKI KAZUO</creator><creatorcontrib>MATSUZAKI KAZUO</creatorcontrib><description>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device which realizes reduction in a manufacturing cost by cutting the number of photomasks, and its manufacturing method. SOLUTION: An SIMOX substrate is used, wherein an oxide film 8 is formed in a substrate 9 and an n- layer 2 is formed thereon. In the n- layer 2, an n-channel MOSFET (NMOS) and a p-channel MOSFET (PMOS) of a CMOS cell 1 are formed isolated and independent via an isolation groove, respectively. A p-well region 3 and an n+ source region 4 are formed to self-align using a gate electrode 12 as a mask. By using the isolation groove, it is possible to eliminate the need for an LOCOS oxide film and a stopper region, and to greatly cut the number of photomasks necessary in a manufacturing process by the application of the isolation groove formation and self alignment.</description><edition>7</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2002</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20020614&DB=EPODOC&CC=JP&NR=2002170957A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76516</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20020614&DB=EPODOC&CC=JP&NR=2002170957A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MATSUZAKI KAZUO</creatorcontrib><title>SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURING METHOD</title><description>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device which realizes reduction in a manufacturing cost by cutting the number of photomasks, and its manufacturing method. SOLUTION: An SIMOX substrate is used, wherein an oxide film 8 is formed in a substrate 9 and an n- layer 2 is formed thereon. In the n- layer 2, an n-channel MOSFET (NMOS) and a p-channel MOSFET (PMOS) of a CMOS cell 1 are formed isolated and independent via an isolation groove, respectively. A p-well region 3 and an n+ source region 4 are formed to self-align using a gate electrode 12 as a mask. By using the isolation groove, it is possible to eliminate the need for an LOCOS oxide film and a stopper region, and to greatly cut the number of photomasks necessary in a manufacturing process by the application of the isolation groove formation and self alignment.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2002</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyrEKwjAQANAsDqL-w-EuxIqUjuHu2p6QRNKLaykSJ9FC_X9c_ACnt7y1oYG9YAyUUWMCCcpdcsoEKAmzKBDfBBlcIBAdwLuQW4eak4QOPGsfaWtWj-m5lN3Pjdm3rNgfyvweyzJP9_Iqn_FyraytjrVtzrU7_ZW-yKEsYg</recordid><startdate>20020614</startdate><enddate>20020614</enddate><creator>MATSUZAKI KAZUO</creator><scope>EVB</scope></search><sort><creationdate>20020614</creationdate><title>SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURING METHOD</title><author>MATSUZAKI KAZUO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2002170957A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2002</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>MATSUZAKI KAZUO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MATSUZAKI KAZUO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURING METHOD</title><date>2002-06-14</date><risdate>2002</risdate><abstract>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device which realizes reduction in a manufacturing cost by cutting the number of photomasks, and its manufacturing method. SOLUTION: An SIMOX substrate is used, wherein an oxide film 8 is formed in a substrate 9 and an n- layer 2 is formed thereon. In the n- layer 2, an n-channel MOSFET (NMOS) and a p-channel MOSFET (PMOS) of a CMOS cell 1 are formed isolated and independent via an isolation groove, respectively. A p-well region 3 and an n+ source region 4 are formed to self-align using a gate electrode 12 as a mask. By using the isolation groove, it is possible to eliminate the need for an LOCOS oxide film and a stopper region, and to greatly cut the number of photomasks necessary in a manufacturing process by the application of the isolation groove formation and self alignment.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURING METHOD |
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