METHOD FOR MANUFACTURING VERTICAL MOS TRANSISTOR

PROBLEM TO BE SOLVED: To resolve the problems of chip yield being decreased and manufacturing cost being increased since the chip will be a defective, even if there is a transistor with only one defective in the chip in a conventional vertical MOS transistor where a single source pad is provided for...

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1. Verfasser:	KATSUTA HIDESATO
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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