METHOD FOR MANUFACTURING VERTICAL MOS TRANSISTOR
PROBLEM TO BE SOLVED: To resolve the problems of chip yield being decreased and manufacturing cost being increased since the chip will be a defective, even if there is a transistor with only one defective in the chip in a conventional vertical MOS transistor where a single source pad is provided for...
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| creator | KATSUTA HIDESATO |
| description | PROBLEM TO BE SOLVED: To resolve the problems of chip yield being decreased and manufacturing cost being increased since the chip will be a defective, even if there is a transistor with only one defective in the chip in a conventional vertical MOS transistor where a single source pad is provided for a group of source electrodes in a transistor region of a semiconductor chip and that is manufactured by connecting the source pad of the semiconductor chip considered to be quality goods to a source terminal with a bounding wire. SOLUTION: The semiconductor chip 100 is divided into transistor regions 51, 52 that are more than 2 divisions, and source pads 1, 2 corresponding to each transistor region are provided. Since, if there is only one good product in two transistor regions, it is manufactured by connecting the source pads corresponding to the transistor regions to a source terminal, the disposal rate due to the defectiveness of the semiconductor chip can be reduced and manufacturing costs of product can be reduced. |
| format | Patent |
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SOLUTION: The semiconductor chip 100 is divided into transistor regions 51, 52 that are more than 2 divisions, and source pads 1, 2 corresponding to each transistor region are provided. Since, if there is only one good product in two transistor regions, it is manufactured by connecting the source pads corresponding to the transistor regions to a source terminal, the disposal rate due to the defectiveness of the semiconductor chip can be reduced and manufacturing costs of product can be reduced.</description><edition>7</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2002</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20020412&DB=EPODOC&CC=JP&NR=2002110727A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20020412&DB=EPODOC&CC=JP&NR=2002110727A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KATSUTA HIDESATO</creatorcontrib><title>METHOD FOR MANUFACTURING VERTICAL MOS TRANSISTOR</title><description>PROBLEM TO BE SOLVED: To resolve the problems of chip yield being decreased and manufacturing cost being increased since the chip will be a defective, even if there is a transistor with only one defective in the chip in a conventional vertical MOS transistor where a single source pad is provided for a group of source electrodes in a transistor region of a semiconductor chip and that is manufactured by connecting the source pad of the semiconductor chip considered to be quality goods to a source terminal with a bounding wire. SOLUTION: The semiconductor chip 100 is divided into transistor regions 51, 52 that are more than 2 divisions, and source pads 1, 2 corresponding to each transistor region are provided. Since, if there is only one good product in two transistor regions, it is manufactured by connecting the source pads corresponding to the transistor regions to a source terminal, the disposal rate due to the defectiveness of the semiconductor chip can be reduced and manufacturing costs of product can be reduced.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2002</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDDwdQ3x8HdRcPMPUvB19At1c3QOCQ3y9HNXCHMNCvF0dvRR8PUPVggJcvQL9gwO8Q_iYWBNS8wpTuWF0twMSm6uIc4euqkF-fGpxQWJyal5qSXxXgFGBgZGhoYG5kbmjsZEKQIAlfgm9Q</recordid><startdate>20020412</startdate><enddate>20020412</enddate><creator>KATSUTA HIDESATO</creator><scope>EVB</scope></search><sort><creationdate>20020412</creationdate><title>METHOD FOR MANUFACTURING VERTICAL MOS TRANSISTOR</title><author>KATSUTA HIDESATO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2002110727A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2002</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>KATSUTA HIDESATO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KATSUTA HIDESATO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>METHOD FOR MANUFACTURING VERTICAL MOS TRANSISTOR</title><date>2002-04-12</date><risdate>2002</risdate><abstract>PROBLEM TO BE SOLVED: To resolve the problems of chip yield being decreased and manufacturing cost being increased since the chip will be a defective, even if there is a transistor with only one defective in the chip in a conventional vertical MOS transistor where a single source pad is provided for a group of source electrodes in a transistor region of a semiconductor chip and that is manufactured by connecting the source pad of the semiconductor chip considered to be quality goods to a source terminal with a bounding wire. SOLUTION: The semiconductor chip 100 is divided into transistor regions 51, 52 that are more than 2 divisions, and source pads 1, 2 corresponding to each transistor region are provided. Since, if there is only one good product in two transistor regions, it is manufactured by connecting the source pads corresponding to the transistor regions to a source terminal, the disposal rate due to the defectiveness of the semiconductor chip can be reduced and manufacturing costs of product can be reduced.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | METHOD FOR MANUFACTURING VERTICAL MOS TRANSISTOR |
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