DIGITAL PROCESSING PHASE LOCKED LOOP CIRCUIT

PROBLEM TO BE SOLVED: To provide a digital processing phase locked loop circuit that can reduce a synchronization lock time required when a frequency deviation takes place in a built-in oscillator. SOLUTION: The digital processing phase locked loop circuit employs a frequency deviation correction processing consisting of a means that uses a voltage-frequency characteristic of a voltage controlled oscillator stored in a ROM 4 to measure a phase difference per a prescribed unit time, of a means that obtains a frequency deviation from the phase difference, of a means that uses a database to obtain a center voltage value resulting from correcting the frequency deviation, and of a means that gives the obtained center voltage to the voltage controlled oscillator and starts synchronization locking and the digital processing phase locked loop circuit applies the processing to the frequency deviation so as to reduce the synchronization lock time.