SEMICONDUCTOR MEMORY, REDUNDANCY CIRCUIT AND REDUNDANCY METHOD FOR THIS DEVICE
PROBLEM TO BE SOLVED: To improve a redundancy rate at the time of performing column redundancy operation. SOLUTION: This device is provided with a control signal generating circuit 52 for generating block control signals of the prescribed number by dividing plural memory cell array blocks into group...
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| creator | TEI GENTAKU KIN KEIO |
| description | PROBLEM TO BE SOLVED: To improve a redundancy rate at the time of performing column redundancy operation. SOLUTION: This device is provided with a control signal generating circuit 52 for generating block control signals of the prescribed number by dividing plural memory cell array blocks into groups of the prescribed number for each of redundant column selecting signal lines of the prescribed numbers, defective redundant enable-signal generating circuit 54-1 to 54-i of the prescribed numbers for generating redundant enable-signals of the prescribed numbers when defective addresses for each of block control signals of the prescribed numbers are set and those defective addresses are inputted, and a selecting circuit 50 for outputting each of the redundant enable-signals of the prescribed numbers as a redundant column selecting signal responding to each of the block control signals of the prescribed numbers. Plural memory cell array blocks are divided into groups of the prescribed numbers for each of redundant column selecting signals so that redundancy operation can be performed. |
| format | Patent |
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SOLUTION: This device is provided with a control signal generating circuit 52 for generating block control signals of the prescribed number by dividing plural memory cell array blocks into groups of the prescribed number for each of redundant column selecting signal lines of the prescribed numbers, defective redundant enable-signal generating circuit 54-1 to 54-i of the prescribed numbers for generating redundant enable-signals of the prescribed numbers when defective addresses for each of block control signals of the prescribed numbers are set and those defective addresses are inputted, and a selecting circuit 50 for outputting each of the redundant enable-signals of the prescribed numbers as a redundant column selecting signal responding to each of the block control signals of the prescribed numbers. Plural memory cell array blocks are divided into groups of the prescribed numbers for each of redundant column selecting signals so that redundancy operation can be performed.</description><edition>7</edition><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2001</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20011019&DB=EPODOC&CC=JP&NR=2001291396A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20011019&DB=EPODOC&CC=JP&NR=2001291396A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>TEI GENTAKU</creatorcontrib><creatorcontrib>KIN KEIO</creatorcontrib><title>SEMICONDUCTOR MEMORY, REDUNDANCY CIRCUIT AND REDUNDANCY METHOD FOR THIS DEVICE</title><description>PROBLEM TO BE SOLVED: To improve a redundancy rate at the time of performing column redundancy operation. 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Plural memory cell array blocks are divided into groups of the prescribed numbers for each of redundant column selecting signals so that redundancy operation can be performed.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2001</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZPALdvX1dPb3cwl1DvEPUvB19fUPitRRCHJ1CfVzcfRzjlRw9gxyDvUMUXD0c0EW9nUN8fB3UXADagrx8AxWcHEN83R25WFgTUvMKU7lhdLcDEpuriHOHrqpBfnxqcUFicmpeakl8V4BRgYGhkaWhsaWZo7GRCkCAIRVLv8</recordid><startdate>20011019</startdate><enddate>20011019</enddate><creator>TEI GENTAKU</creator><creator>KIN KEIO</creator><scope>EVB</scope></search><sort><creationdate>20011019</creationdate><title>SEMICONDUCTOR MEMORY, REDUNDANCY CIRCUIT AND REDUNDANCY METHOD FOR THIS DEVICE</title><author>TEI GENTAKU ; KIN KEIO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2001291396A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2001</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>TEI GENTAKU</creatorcontrib><creatorcontrib>KIN KEIO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>TEI GENTAKU</au><au>KIN KEIO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR MEMORY, REDUNDANCY CIRCUIT AND REDUNDANCY METHOD FOR THIS DEVICE</title><date>2001-10-19</date><risdate>2001</risdate><abstract>PROBLEM TO BE SOLVED: To improve a redundancy rate at the time of performing column redundancy operation. SOLUTION: This device is provided with a control signal generating circuit 52 for generating block control signals of the prescribed number by dividing plural memory cell array blocks into groups of the prescribed number for each of redundant column selecting signal lines of the prescribed numbers, defective redundant enable-signal generating circuit 54-1 to 54-i of the prescribed numbers for generating redundant enable-signals of the prescribed numbers when defective addresses for each of block control signals of the prescribed numbers are set and those defective addresses are inputted, and a selecting circuit 50 for outputting each of the redundant enable-signals of the prescribed numbers as a redundant column selecting signal responding to each of the block control signals of the prescribed numbers. Plural memory cell array blocks are divided into groups of the prescribed numbers for each of redundant column selecting signals so that redundancy operation can be performed.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INFORMATION STORAGE PHYSICS STATIC STORES |
| title | SEMICONDUCTOR MEMORY, REDUNDANCY CIRCUIT AND REDUNDANCY METHOD FOR THIS DEVICE |
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