TEST METHOD FOR VOLATILE MEMORY
PROBLEM TO BE SOLVED: To provide a test method for shortening a test time of a volatile memory. SOLUTION: Instaed of a conventional access test, data in which all bits are '0' of a data bus connected to a volatile memory is written in a volatile memory, only arbitrary 1 bit of a data bus c...
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | KAMIYA TOSHIZANE |
| description | PROBLEM TO BE SOLVED: To provide a test method for shortening a test time of a volatile memory. SOLUTION: Instaed of a conventional access test, data in which all bits are '0' of a data bus connected to a volatile memory is written in a volatile memory, only arbitrary 1 bit of a data bus connected to the volatile memory is level-changed from '0' to '1' and written in the volatile memory, states of the bits before and after of the level-change and other bits are read and state change is detected, when a state is changed, it is judged that the surrounding of the bit is defective, while defect of the surrounding of the data bus connected to the volatile memory is detected by performed the above operation for all bits of the data bus connected to the volatile memory. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2001256797A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2001256797A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2001256797A3</originalsourceid><addsrcrecordid>eNrjZJAPcQ0OUfB1DfHwd1Fw8w9SCPP3cQzx9HEFivn6B0XyMLCmJeYUp_JCaW4GJTfXEGcP3dSC_PjU4oLE5NS81JJ4rwAjAwNDI1Mzc0tzR2OiFAEAGnQiKQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>TEST METHOD FOR VOLATILE MEMORY</title><source>esp@cenet</source><creator>KAMIYA TOSHIZANE</creator><creatorcontrib>KAMIYA TOSHIZANE</creatorcontrib><description>PROBLEM TO BE SOLVED: To provide a test method for shortening a test time of a volatile memory. SOLUTION: Instaed of a conventional access test, data in which all bits are '0' of a data bus connected to a volatile memory is written in a volatile memory, only arbitrary 1 bit of a data bus connected to the volatile memory is level-changed from '0' to '1' and written in the volatile memory, states of the bits before and after of the level-change and other bits are read and state change is detected, when a state is changed, it is judged that the surrounding of the bit is defective, while defect of the surrounding of the data bus connected to the volatile memory is detected by performed the above operation for all bits of the data bus connected to the volatile memory.</description><edition>7</edition><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; INFORMATION STORAGE ; MEASURING ; MEASURING ELECTRIC VARIABLES ; MEASURING MAGNETIC VARIABLES ; PHYSICS ; STATIC STORES ; TESTING</subject><creationdate>2001</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20010921&DB=EPODOC&CC=JP&NR=2001256797A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20010921&DB=EPODOC&CC=JP&NR=2001256797A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KAMIYA TOSHIZANE</creatorcontrib><title>TEST METHOD FOR VOLATILE MEMORY</title><description>PROBLEM TO BE SOLVED: To provide a test method for shortening a test time of a volatile memory. SOLUTION: Instaed of a conventional access test, data in which all bits are '0' of a data bus connected to a volatile memory is written in a volatile memory, only arbitrary 1 bit of a data bus connected to the volatile memory is level-changed from '0' to '1' and written in the volatile memory, states of the bits before and after of the level-change and other bits are read and state change is detected, when a state is changed, it is judged that the surrounding of the bit is defective, while defect of the surrounding of the data bus connected to the volatile memory is detected by performed the above operation for all bits of the data bus connected to the volatile memory.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>INFORMATION STORAGE</subject><subject>MEASURING</subject><subject>MEASURING ELECTRIC VARIABLES</subject><subject>MEASURING MAGNETIC VARIABLES</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><subject>TESTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2001</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJAPcQ0OUfB1DfHwd1Fw8w9SCPP3cQzx9HEFivn6B0XyMLCmJeYUp_JCaW4GJTfXEGcP3dSC_PjU4oLE5NS81JJ4rwAjAwNDI1Mzc0tzR2OiFAEAGnQiKQ</recordid><startdate>20010921</startdate><enddate>20010921</enddate><creator>KAMIYA TOSHIZANE</creator><scope>EVB</scope></search><sort><creationdate>20010921</creationdate><title>TEST METHOD FOR VOLATILE MEMORY</title><author>KAMIYA TOSHIZANE</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2001256797A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2001</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>INFORMATION STORAGE</topic><topic>MEASURING</topic><topic>MEASURING ELECTRIC VARIABLES</topic><topic>MEASURING MAGNETIC VARIABLES</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><topic>TESTING</topic><toplevel>online_resources</toplevel><creatorcontrib>KAMIYA TOSHIZANE</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KAMIYA TOSHIZANE</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>TEST METHOD FOR VOLATILE MEMORY</title><date>2001-09-21</date><risdate>2001</risdate><abstract>PROBLEM TO BE SOLVED: To provide a test method for shortening a test time of a volatile memory. SOLUTION: Instaed of a conventional access test, data in which all bits are '0' of a data bus connected to a volatile memory is written in a volatile memory, only arbitrary 1 bit of a data bus connected to the volatile memory is level-changed from '0' to '1' and written in the volatile memory, states of the bits before and after of the level-change and other bits are read and state change is detected, when a state is changed, it is judged that the surrounding of the bit is defective, while defect of the surrounding of the data bus connected to the volatile memory is detected by performed the above operation for all bits of the data bus connected to the volatile memory.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_epo_espacenet_JP2001256797A |
| source | esp@cenet |
| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INFORMATION STORAGE MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS STATIC STORES TESTING |
| title | TEST METHOD FOR VOLATILE MEMORY |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-03T23%3A36%3A01IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=KAMIYA%20TOSHIZANE&rft.date=2001-09-21&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJP2001256797A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |