SIGNAL PROCESSING CIRCUIT FOR VTR
PROBLEM TO BE SOLVED: To provide a signal processing circuit for a VTR that attains reproduction frequency conversion while eliminating color crosstalk with a simple configuration and requires no adjustment. SOLUTION: A delay circuit delays a 1st reproduced color under signal by one or two horizonta...
Gespeichert in:
Hauptverfasser: | , , , , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | YAMAZAKI KOICHI ISHIHARA SHINICHI TAKAHATA MAKOTO JIN TAKASHI YAMAUCHI KIYONARI |
description | PROBLEM TO BE SOLVED: To provide a signal processing circuit for a VTR that attains reproduction frequency conversion while eliminating color crosstalk with a simple configuration and requires no adjustment. SOLUTION: A delay circuit delays a 1st reproduced color under signal by one or two horizontal periods, 1st and 2nd frequency conversion circuits convert the frequency of the delayed 2nd and 1st reproduced color under signals respectively into a frequency of a standard color signal, a frequency divider circuit divides 2n-sets (n is a natural number) of oscillated frequency signals of a carrier for the frequency conversion into the carrier frequency to form 4 carries having phases of 0 deg., 90 deg., 180 deg., and 270 deg., a changeover circuit respectively supplies the carrier to the 1st and 2nd frequency conversion circuits, where two frequency- converted signals are subtracted or added in phase or in opposite phase to eliminate color crosstalk between tracks. The delay circuit consisting of a CCD or the like to delay the under color signal has a lower clock frequency and can simply be configured and a no adjustment circuit can be realized. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2001177847A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2001177847A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2001177847A3</originalsourceid><addsrcrecordid>eNrjZFAM9nT3c_RRCAjyd3YNDvb0c1dw9gxyDvUMUXDzD1IICwniYWBNS8wpTuWF0twMSm6uIc4euqkF-fGpxQWJyal5qSXxXgFGBgaGhubmFibmjsZEKQIAYbYitw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SIGNAL PROCESSING CIRCUIT FOR VTR</title><source>esp@cenet</source><creator>YAMAZAKI KOICHI ; ISHIHARA SHINICHI ; TAKAHATA MAKOTO ; JIN TAKASHI ; YAMAUCHI KIYONARI</creator><creatorcontrib>YAMAZAKI KOICHI ; ISHIHARA SHINICHI ; TAKAHATA MAKOTO ; JIN TAKASHI ; YAMAUCHI KIYONARI</creatorcontrib><description>PROBLEM TO BE SOLVED: To provide a signal processing circuit for a VTR that attains reproduction frequency conversion while eliminating color crosstalk with a simple configuration and requires no adjustment. SOLUTION: A delay circuit delays a 1st reproduced color under signal by one or two horizontal periods, 1st and 2nd frequency conversion circuits convert the frequency of the delayed 2nd and 1st reproduced color under signals respectively into a frequency of a standard color signal, a frequency divider circuit divides 2n-sets (n is a natural number) of oscillated frequency signals of a carrier for the frequency conversion into the carrier frequency to form 4 carries having phases of 0 deg., 90 deg., 180 deg., and 270 deg., a changeover circuit respectively supplies the carrier to the 1st and 2nd frequency conversion circuits, where two frequency- converted signals are subtracted or added in phase or in opposite phase to eliminate color crosstalk between tracks. The delay circuit consisting of a CCD or the like to delay the under color signal has a lower clock frequency and can simply be configured and a no adjustment circuit can be realized.</description><edition>7</edition><language>eng</language><subject>ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRICITY ; PICTORIAL COMMUNICATION, e.g. TELEVISION</subject><creationdate>2001</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20010629&DB=EPODOC&CC=JP&NR=2001177847A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20010629&DB=EPODOC&CC=JP&NR=2001177847A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>YAMAZAKI KOICHI</creatorcontrib><creatorcontrib>ISHIHARA SHINICHI</creatorcontrib><creatorcontrib>TAKAHATA MAKOTO</creatorcontrib><creatorcontrib>JIN TAKASHI</creatorcontrib><creatorcontrib>YAMAUCHI KIYONARI</creatorcontrib><title>SIGNAL PROCESSING CIRCUIT FOR VTR</title><description>PROBLEM TO BE SOLVED: To provide a signal processing circuit for a VTR that attains reproduction frequency conversion while eliminating color crosstalk with a simple configuration and requires no adjustment. SOLUTION: A delay circuit delays a 1st reproduced color under signal by one or two horizontal periods, 1st and 2nd frequency conversion circuits convert the frequency of the delayed 2nd and 1st reproduced color under signals respectively into a frequency of a standard color signal, a frequency divider circuit divides 2n-sets (n is a natural number) of oscillated frequency signals of a carrier for the frequency conversion into the carrier frequency to form 4 carries having phases of 0 deg., 90 deg., 180 deg., and 270 deg., a changeover circuit respectively supplies the carrier to the 1st and 2nd frequency conversion circuits, where two frequency- converted signals are subtracted or added in phase or in opposite phase to eliminate color crosstalk between tracks. The delay circuit consisting of a CCD or the like to delay the under color signal has a lower clock frequency and can simply be configured and a no adjustment circuit can be realized.</description><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRICITY</subject><subject>PICTORIAL COMMUNICATION, e.g. TELEVISION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2001</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFAM9nT3c_RRCAjyd3YNDvb0c1dw9gxyDvUMUXDzD1IICwniYWBNS8wpTuWF0twMSm6uIc4euqkF-fGpxQWJyal5qSXxXgFGBgaGhubmFibmjsZEKQIAYbYitw</recordid><startdate>20010629</startdate><enddate>20010629</enddate><creator>YAMAZAKI KOICHI</creator><creator>ISHIHARA SHINICHI</creator><creator>TAKAHATA MAKOTO</creator><creator>JIN TAKASHI</creator><creator>YAMAUCHI KIYONARI</creator><scope>EVB</scope></search><sort><creationdate>20010629</creationdate><title>SIGNAL PROCESSING CIRCUIT FOR VTR</title><author>YAMAZAKI KOICHI ; ISHIHARA SHINICHI ; TAKAHATA MAKOTO ; JIN TAKASHI ; YAMAUCHI KIYONARI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2001177847A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2001</creationdate><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRICITY</topic><topic>PICTORIAL COMMUNICATION, e.g. TELEVISION</topic><toplevel>online_resources</toplevel><creatorcontrib>YAMAZAKI KOICHI</creatorcontrib><creatorcontrib>ISHIHARA SHINICHI</creatorcontrib><creatorcontrib>TAKAHATA MAKOTO</creatorcontrib><creatorcontrib>JIN TAKASHI</creatorcontrib><creatorcontrib>YAMAUCHI KIYONARI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>YAMAZAKI KOICHI</au><au>ISHIHARA SHINICHI</au><au>TAKAHATA MAKOTO</au><au>JIN TAKASHI</au><au>YAMAUCHI KIYONARI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SIGNAL PROCESSING CIRCUIT FOR VTR</title><date>2001-06-29</date><risdate>2001</risdate><abstract>PROBLEM TO BE SOLVED: To provide a signal processing circuit for a VTR that attains reproduction frequency conversion while eliminating color crosstalk with a simple configuration and requires no adjustment. SOLUTION: A delay circuit delays a 1st reproduced color under signal by one or two horizontal periods, 1st and 2nd frequency conversion circuits convert the frequency of the delayed 2nd and 1st reproduced color under signals respectively into a frequency of a standard color signal, a frequency divider circuit divides 2n-sets (n is a natural number) of oscillated frequency signals of a carrier for the frequency conversion into the carrier frequency to form 4 carries having phases of 0 deg., 90 deg., 180 deg., and 270 deg., a changeover circuit respectively supplies the carrier to the 1st and 2nd frequency conversion circuits, where two frequency- converted signals are subtracted or added in phase or in opposite phase to eliminate color crosstalk between tracks. The delay circuit consisting of a CCD or the like to delay the under color signal has a lower clock frequency and can simply be configured and a no adjustment circuit can be realized.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_epo_espacenet_JP2001177847A |
source | esp@cenet |
subjects | ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY PICTORIAL COMMUNICATION, e.g. TELEVISION |
title | SIGNAL PROCESSING CIRCUIT FOR VTR |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-29T03%3A00%3A12IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=YAMAZAKI%20KOICHI&rft.date=2001-06-29&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJP2001177847A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |