SUBSTRATE FOR MULTIPLE BOARDS AND WIRING BOARD

PROBLEM TO BE SOLVED: To facilitate measurement and inspection of a circuit by perfectly insulating circuits between circuit boards provided with castellation structure formed on substrate for multiple boards. SOLUTION: Many circuit boards Aij are formed on substrate for multiple boards. On the surf...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: NAKA KATSUHIKO, NAKAI TOSHIHIRO
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator NAKA KATSUHIKO
NAKAI TOSHIHIRO
description PROBLEM TO BE SOLVED: To facilitate measurement and inspection of a circuit by perfectly insulating circuits between circuit boards provided with castellation structure formed on substrate for multiple boards. SOLUTION: Many circuit boards Aij are formed on substrate for multiple boards. On the surface of the board 11, dividing lines 12 are formed along boundary lines of the circuit boards Aij, and through holes 13 are formed along the dividing lines 12. On the inner peripheral surface of each of the through holes 13, two castellation conductors are separately formed opposite to each other via the dividing line 12. On the single surface of the board 11, I/O lands 15 of each of the castellation conductors are separately formed opposite to each other via the dividing line 12. In the board 11, circuits of the individual circuit boards Aij are perfectly insulated before division by the dividing lines 12, so that measurement and inspection of circuit characteristics of the individual circuit boards Aij are enabled before division.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2001068823A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2001068823A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2001068823A3</originalsourceid><addsrcrecordid>eNrjZNALDnUKDglyDHFVcPMPUvAN9QnxDPBxVXDydwxyCVZw9HNRCPcM8vRzh4jwMLCmJeYUp_JCaW4GJTfXEGcP3dSC_PjU4oLE5NS81JJ4rwAjAwNDAzMLCyNjR2OiFAEALDImGw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SUBSTRATE FOR MULTIPLE BOARDS AND WIRING BOARD</title><source>esp@cenet</source><creator>NAKA KATSUHIKO ; NAKAI TOSHIHIRO</creator><creatorcontrib>NAKA KATSUHIKO ; NAKAI TOSHIHIRO</creatorcontrib><description>PROBLEM TO BE SOLVED: To facilitate measurement and inspection of a circuit by perfectly insulating circuits between circuit boards provided with castellation structure formed on substrate for multiple boards. SOLUTION: Many circuit boards Aij are formed on substrate for multiple boards. On the surface of the board 11, dividing lines 12 are formed along boundary lines of the circuit boards Aij, and through holes 13 are formed along the dividing lines 12. On the inner peripheral surface of each of the through holes 13, two castellation conductors are separately formed opposite to each other via the dividing line 12. On the single surface of the board 11, I/O lands 15 of each of the castellation conductors are separately formed opposite to each other via the dividing line 12. In the board 11, circuits of the individual circuit boards Aij are perfectly insulated before division by the dividing lines 12, so that measurement and inspection of circuit characteristics of the individual circuit boards Aij are enabled before division.</description><edition>7</edition><language>eng</language><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; PRINTED CIRCUITS</subject><creationdate>2001</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20010316&amp;DB=EPODOC&amp;CC=JP&amp;NR=2001068823A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20010316&amp;DB=EPODOC&amp;CC=JP&amp;NR=2001068823A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>NAKA KATSUHIKO</creatorcontrib><creatorcontrib>NAKAI TOSHIHIRO</creatorcontrib><title>SUBSTRATE FOR MULTIPLE BOARDS AND WIRING BOARD</title><description>PROBLEM TO BE SOLVED: To facilitate measurement and inspection of a circuit by perfectly insulating circuits between circuit boards provided with castellation structure formed on substrate for multiple boards. SOLUTION: Many circuit boards Aij are formed on substrate for multiple boards. On the surface of the board 11, dividing lines 12 are formed along boundary lines of the circuit boards Aij, and through holes 13 are formed along the dividing lines 12. On the inner peripheral surface of each of the through holes 13, two castellation conductors are separately formed opposite to each other via the dividing line 12. On the single surface of the board 11, I/O lands 15 of each of the castellation conductors are separately formed opposite to each other via the dividing line 12. In the board 11, circuits of the individual circuit boards Aij are perfectly insulated before division by the dividing lines 12, so that measurement and inspection of circuit characteristics of the individual circuit boards Aij are enabled before division.</description><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>PRINTED CIRCUITS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2001</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNALDnUKDglyDHFVcPMPUvAN9QnxDPBxVXDydwxyCVZw9HNRCPcM8vRzh4jwMLCmJeYUp_JCaW4GJTfXEGcP3dSC_PjU4oLE5NS81JJ4rwAjAwNDAzMLCyNjR2OiFAEALDImGw</recordid><startdate>20010316</startdate><enddate>20010316</enddate><creator>NAKA KATSUHIKO</creator><creator>NAKAI TOSHIHIRO</creator><scope>EVB</scope></search><sort><creationdate>20010316</creationdate><title>SUBSTRATE FOR MULTIPLE BOARDS AND WIRING BOARD</title><author>NAKA KATSUHIKO ; NAKAI TOSHIHIRO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2001068823A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2001</creationdate><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>PRINTED CIRCUITS</topic><toplevel>online_resources</toplevel><creatorcontrib>NAKA KATSUHIKO</creatorcontrib><creatorcontrib>NAKAI TOSHIHIRO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>NAKA KATSUHIKO</au><au>NAKAI TOSHIHIRO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SUBSTRATE FOR MULTIPLE BOARDS AND WIRING BOARD</title><date>2001-03-16</date><risdate>2001</risdate><abstract>PROBLEM TO BE SOLVED: To facilitate measurement and inspection of a circuit by perfectly insulating circuits between circuit boards provided with castellation structure formed on substrate for multiple boards. SOLUTION: Many circuit boards Aij are formed on substrate for multiple boards. On the surface of the board 11, dividing lines 12 are formed along boundary lines of the circuit boards Aij, and through holes 13 are formed along the dividing lines 12. On the inner peripheral surface of each of the through holes 13, two castellation conductors are separately formed opposite to each other via the dividing line 12. On the single surface of the board 11, I/O lands 15 of each of the castellation conductors are separately formed opposite to each other via the dividing line 12. In the board 11, circuits of the individual circuit boards Aij are perfectly insulated before division by the dividing lines 12, so that measurement and inspection of circuit characteristics of the individual circuit boards Aij are enabled before division.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_JP2001068823A
source esp@cenet
subjects CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
PRINTED CIRCUITS
title SUBSTRATE FOR MULTIPLE BOARDS AND WIRING BOARD
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-23T17%3A05%3A09IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=NAKA%20KATSUHIKO&rft.date=2001-03-16&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJP2001068823A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true