SEMICONDUCTOR MEMORY

PROBLEM TO BE SOLVED: To reduce power consumption at the time of write operation of a flash memory or the like having AND array structure and to reduce chip size. SOLUTION: A flash memory or the like comprises memory cells MC of a two layer gate structure type being lattice-arranged, and is provided with a pair of memory arrays ARYUR and ARYDR of which one side array is made an activation state selectively and a sense latch SLR including unit sense latches USL1-USLn. And at the time of write operation, internal voltage V1 of which an absolute value is higher than write voltage by at least threshold voltage of a transfer MOSFETN3 or more is applied to a gate of the transfer MOSFETN3 corresponding to the memory array ARYUR, for example, being the activation state, and internal voltage V2 of which the absolute value is lower than the write voltage is applied to the gate of a transfer MOSFETN4 corresponding to the memory array ARYDR, for example, being a non-activation state.