RESET CIRCUIT AND PLL FREQUENCY SYNTHESIZER

PROBLEM TO BE SOLVED: To obtain a frequency synthesizer by eliminating a delay in a PLL operation time after releasing power saving so as not to delay a lockup time. SOLUTION: A control circuit 23 provided to a reset circuit 21 outputs a set signal S or a reset signal R to a delay circuit 22 to make...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	TAKEGAWA KOUJI, AOKI KOUKI
Format:	Patent
Sprache:	eng
Schlagworte:	AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES BASIC ELECTRONIC CIRCUITRY DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TOANOTHER ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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