SEMICONDUCTOR MEMORY

PROBLEM TO BE SOLVED: To reduce the number of pads used for test mode entry. SOLUTION: Only a pad 11A for clock signal and a pad 11B for input data are connected to a serial register 9 of this semiconductor memory. Input data are successively written in a M bit serial register 9 one bit by one bit....

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Hauptverfasser:	KUWAGATA MASAAKI, MAGOME KOICHI
Format:	Patent
Sprache:	eng
Schlagworte:	INFORMATION STORAGE MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS STATIC STORES TESTING
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creator	KUWAGATA MASAAKI MAGOME KOICHI
description	PROBLEM TO BE SOLVED: To reduce the number of pads used for test mode entry. SOLUTION: Only a pad 11A for clock signal and a pad 11B for input data are connected to a serial register 9 of this semiconductor memory. Input data are successively written in a M bit serial register 9 one bit by one bit. When upper (m) bits of the serial register 9 indicates an address take-in code, an address transfer signal and an address take-in signal are made an enable-state, lower M-m bits of the serial register are transferred and taken in test signal output circuits 6-1, 6-2,... 6-N as a test address signal.
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Input data are successively written in a M bit serial register 9 one bit by one bit. When upper (m) bits of the serial register 9 indicates an address take-in code, an address transfer signal and an address take-in signal are made an enable-state, lower M-m bits of the serial register are transferred and taken in test signal output circuits 6-1, 6-2,... 6-N as a test address signal.</description><edition>7</edition><language>eng</language><subject>INFORMATION STORAGE ; MEASURING ; MEASURING ELECTRIC VARIABLES ; MEASURING MAGNETIC VARIABLES ; PHYSICS ; STATIC STORES ; TESTING</subject><creationdate>2000</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20000914&DB=EPODOC&CC=JP&NR=2000251497A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25566,76549</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20000914&DB=EPODOC&CC=JP&NR=2000251497A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KUWAGATA MASAAKI</creatorcontrib><creatorcontrib>MAGOME KOICHI</creatorcontrib><title>SEMICONDUCTOR MEMORY</title><description>PROBLEM TO BE SOLVED: To reduce the number of pads used for test mode entry. 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When upper (m) bits of the serial register 9 indicates an address take-in code, an address transfer signal and an address take-in signal are made an enable-state, lower M-m bits of the serial register are transferred and taken in test signal output circuits 6-1, 6-2,... 6-N as a test address signal.</description><subject>INFORMATION STORAGE</subject><subject>MEASURING</subject><subject>MEASURING ELECTRIC VARIABLES</subject><subject>MEASURING MAGNETIC VARIABLES</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><subject>TESTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2000</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBAJdvX1dPb3cwl1DvEPUvB19fUPiuRhYE1LzClO5YXS3AxKbq4hzh66qQX58anFBYnJqXmpJfFeAUYGBgZGpoYmluaOxkQpAgDLkB9D</recordid><startdate>20000914</startdate><enddate>20000914</enddate><creator>KUWAGATA MASAAKI</creator><creator>MAGOME KOICHI</creator><scope>EVB</scope></search><sort><creationdate>20000914</creationdate><title>SEMICONDUCTOR MEMORY</title><author>KUWAGATA MASAAKI ; MAGOME KOICHI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2000251497A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2000</creationdate><topic>INFORMATION STORAGE</topic><topic>MEASURING</topic><topic>MEASURING ELECTRIC VARIABLES</topic><topic>MEASURING MAGNETIC VARIABLES</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><topic>TESTING</topic><toplevel>online_resources</toplevel><creatorcontrib>KUWAGATA MASAAKI</creatorcontrib><creatorcontrib>MAGOME KOICHI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KUWAGATA MASAAKI</au><au>MAGOME KOICHI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR MEMORY</title><date>2000-09-14</date><risdate>2000</risdate><abstract>PROBLEM TO BE SOLVED: To reduce the number of pads used for test mode entry. SOLUTION: Only a pad 11A for clock signal and a pad 11B for input data are connected to a serial register 9 of this semiconductor memory. Input data are successively written in a M bit serial register 9 one bit by one bit. When upper (m) bits of the serial register 9 indicates an address take-in code, an address transfer signal and an address take-in signal are made an enable-state, lower M-m bits of the serial register are transferred and taken in test signal output circuits 6-1, 6-2,... 6-N as a test address signal.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record>
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subjects	INFORMATION STORAGE MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS STATIC STORES TESTING
title	SEMICONDUCTOR MEMORY
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