TRENCH ELEMENT SOLATION METHOD FOR SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR ELEMENT USING THE SAME

PROBLEM TO BE SOLVED: To suppress occurrence of dents in a trench element isolation process by forming a trench etching mask pattern on a semiconductor substrate, forming over the entire surface of the semiconductor substrate, a dent-preventing film on the sidwall of the trench etching mask pattern,...

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Hauptverfasser: KO INSHIAKU, KIN SEII, AHN DONG HUL, PARK MOON-HAN, RI KINSHU, KO YANSAN, BOKU TAISHO
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creator KO INSHIAKU
KIN SEII
AHN DONG HUL
PARK MOON-HAN
RI KINSHU
KO YANSAN
BOKU TAISHO
description PROBLEM TO BE SOLVED: To suppress occurrence of dents in a trench element isolation process by forming a trench etching mask pattern on a semiconductor substrate, forming over the entire surface of the semiconductor substrate, a dent-preventing film on the sidwall of the trench etching mask pattern, and depositing a liner layer on the dent-preventing film. SOLUTION: A part of a semiconductor substrate 100 is etched with a mask pattern 104 as a mask to form a trench 106, the inside wall of which is thermally oxidized to form an in-trench oxide film 108. A dent-preventing film 110 of a CVD oxide film with a film quality which has an etching selection ratio to a nitride film is deposited on the resulting object where the in-trench oxide film 108 is formed. After a liner layer 112 is formed using a nitride film, a high-temperature oxide film formed at such high temperature as 700-9000 deg.C is deposited, which is further treated with ammonia plasma processing.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2000208609A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2000208609A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2000208609A3</originalsourceid><addsrcrecordid>eNrjZEgMCXL1c_ZQcPVx9XX1C1EI9vdxDPH091PwdQ3x8HdRcPMPUgh29fV09vdzCXUOAfJgKh39XHDIhAZ7-rkrhHi4KgQ7-rryMLCmJeYUp_JCaW4GJTfXEGcP3dSC_PjU4oLE5NS81JJ4rwAjAwMDIwMLMwNLR2OiFAEANOQ0Qw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>TRENCH ELEMENT SOLATION METHOD FOR SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR ELEMENT USING THE SAME</title><source>esp@cenet</source><creator>KO INSHIAKU ; KIN SEII ; AHN DONG HUL ; PARK MOON-HAN ; RI KINSHU ; KO YANSAN ; BOKU TAISHO</creator><creatorcontrib>KO INSHIAKU ; KIN SEII ; AHN DONG HUL ; PARK MOON-HAN ; RI KINSHU ; KO YANSAN ; BOKU TAISHO</creatorcontrib><description>PROBLEM TO BE SOLVED: To suppress occurrence of dents in a trench element isolation process by forming a trench etching mask pattern on a semiconductor substrate, forming over the entire surface of the semiconductor substrate, a dent-preventing film on the sidwall of the trench etching mask pattern, and depositing a liner layer on the dent-preventing film. SOLUTION: A part of a semiconductor substrate 100 is etched with a mask pattern 104 as a mask to form a trench 106, the inside wall of which is thermally oxidized to form an in-trench oxide film 108. A dent-preventing film 110 of a CVD oxide film with a film quality which has an etching selection ratio to a nitride film is deposited on the resulting object where the in-trench oxide film 108 is formed. After a liner layer 112 is formed using a nitride film, a high-temperature oxide film formed at such high temperature as 700-9000 deg.C is deposited, which is further treated with ammonia plasma processing.</description><edition>7</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2000</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20000728&amp;DB=EPODOC&amp;CC=JP&amp;NR=2000208609A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76294</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20000728&amp;DB=EPODOC&amp;CC=JP&amp;NR=2000208609A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KO INSHIAKU</creatorcontrib><creatorcontrib>KIN SEII</creatorcontrib><creatorcontrib>AHN DONG HUL</creatorcontrib><creatorcontrib>PARK MOON-HAN</creatorcontrib><creatorcontrib>RI KINSHU</creatorcontrib><creatorcontrib>KO YANSAN</creatorcontrib><creatorcontrib>BOKU TAISHO</creatorcontrib><title>TRENCH ELEMENT SOLATION METHOD FOR SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR ELEMENT USING THE SAME</title><description>PROBLEM TO BE SOLVED: To suppress occurrence of dents in a trench element isolation process by forming a trench etching mask pattern on a semiconductor substrate, forming over the entire surface of the semiconductor substrate, a dent-preventing film on the sidwall of the trench etching mask pattern, and depositing a liner layer on the dent-preventing film. SOLUTION: A part of a semiconductor substrate 100 is etched with a mask pattern 104 as a mask to form a trench 106, the inside wall of which is thermally oxidized to form an in-trench oxide film 108. A dent-preventing film 110 of a CVD oxide film with a film quality which has an etching selection ratio to a nitride film is deposited on the resulting object where the in-trench oxide film 108 is formed. After a liner layer 112 is formed using a nitride film, a high-temperature oxide film formed at such high temperature as 700-9000 deg.C is deposited, which is further treated with ammonia plasma processing.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2000</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZEgMCXL1c_ZQcPVx9XX1C1EI9vdxDPH091PwdQ3x8HdRcPMPUgh29fV09vdzCXUOAfJgKh39XHDIhAZ7-rkrhHi4KgQ7-rryMLCmJeYUp_JCaW4GJTfXEGcP3dSC_PjU4oLE5NS81JJ4rwAjAwMDIwMLMwNLR2OiFAEANOQ0Qw</recordid><startdate>20000728</startdate><enddate>20000728</enddate><creator>KO INSHIAKU</creator><creator>KIN SEII</creator><creator>AHN DONG HUL</creator><creator>PARK MOON-HAN</creator><creator>RI KINSHU</creator><creator>KO YANSAN</creator><creator>BOKU TAISHO</creator><scope>EVB</scope></search><sort><creationdate>20000728</creationdate><title>TRENCH ELEMENT SOLATION METHOD FOR SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR ELEMENT USING THE SAME</title><author>KO INSHIAKU ; KIN SEII ; AHN DONG HUL ; PARK MOON-HAN ; RI KINSHU ; KO YANSAN ; BOKU TAISHO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2000208609A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2000</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>KO INSHIAKU</creatorcontrib><creatorcontrib>KIN SEII</creatorcontrib><creatorcontrib>AHN DONG HUL</creatorcontrib><creatorcontrib>PARK MOON-HAN</creatorcontrib><creatorcontrib>RI KINSHU</creatorcontrib><creatorcontrib>KO YANSAN</creatorcontrib><creatorcontrib>BOKU TAISHO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KO INSHIAKU</au><au>KIN SEII</au><au>AHN DONG HUL</au><au>PARK MOON-HAN</au><au>RI KINSHU</au><au>KO YANSAN</au><au>BOKU TAISHO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>TRENCH ELEMENT SOLATION METHOD FOR SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR ELEMENT USING THE SAME</title><date>2000-07-28</date><risdate>2000</risdate><abstract>PROBLEM TO BE SOLVED: To suppress occurrence of dents in a trench element isolation process by forming a trench etching mask pattern on a semiconductor substrate, forming over the entire surface of the semiconductor substrate, a dent-preventing film on the sidwall of the trench etching mask pattern, and depositing a liner layer on the dent-preventing film. SOLUTION: A part of a semiconductor substrate 100 is etched with a mask pattern 104 as a mask to form a trench 106, the inside wall of which is thermally oxidized to form an in-trench oxide film 108. A dent-preventing film 110 of a CVD oxide film with a film quality which has an etching selection ratio to a nitride film is deposited on the resulting object where the in-trench oxide film 108 is formed. After a liner layer 112 is formed using a nitride film, a high-temperature oxide film formed at such high temperature as 700-9000 deg.C is deposited, which is further treated with ammonia plasma processing.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title TRENCH ELEMENT SOLATION METHOD FOR SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR ELEMENT USING THE SAME
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