INSULATED GATE BIPOLAR TRANSISTOR MODULE HAVING RESISTANCE TO SHORT-CIRCUITING
PROBLEM TO BE SOLVED: To prevent short-circuit of individual chips from causing damages to the entire module, by forming an eutectic mixed material of a layer which is joined to main electrodes of a silicon semiconductor and which contains silver and silicon. SOLUTION: Semiconductor chips 4 have mai...
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creator | LANG THOMAS DR ZELLER HANS RUDOLF DR |
description | PROBLEM TO BE SOLVED: To prevent short-circuit of individual chips from causing damages to the entire module, by forming an eutectic mixed material of a layer which is joined to main electrodes of a silicon semiconductor and which contains silver and silicon. SOLUTION: Semiconductor chips 4 have main electrodes 5 and 6 which are coated with metal on both of tops and bottoms, and are electrically connected. The semiconductor chips 4 are supported on a conductive substrate 2, and connection pistons are arranged directly on every chips. A layer 7 arranged between the metal joining surfaces adjacent to either the main electrode 5 or the main electrode 6 is easily manufactured from a thin metal chip containing silver, or is applied to the main electrodes as paste. Usually, the thickness of the layer 7 is set to a half or larger than that of the semiconductor chip 4. Silver is suitable for the semiconductor 4 as a mating material of an eutectic material. The eutectic point of AgSi containing silver of 11% by the atomic weight is 835 deg.C, and this is far lower than the melting point of simple substance of silicon. |
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SOLUTION: Semiconductor chips 4 have main electrodes 5 and 6 which are coated with metal on both of tops and bottoms, and are electrically connected. The semiconductor chips 4 are supported on a conductive substrate 2, and connection pistons are arranged directly on every chips. A layer 7 arranged between the metal joining surfaces adjacent to either the main electrode 5 or the main electrode 6 is easily manufactured from a thin metal chip containing silver, or is applied to the main electrodes as paste. Usually, the thickness of the layer 7 is set to a half or larger than that of the semiconductor chip 4. Silver is suitable for the semiconductor 4 as a mating material of an eutectic material. The eutectic point of AgSi containing silver of 11% by the atomic weight is 835 deg.C, and this is far lower than the melting point of simple substance of silicon.</description><edition>7</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2000</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20000411&DB=EPODOC&CC=JP&NR=2000106374A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20000411&DB=EPODOC&CC=JP&NR=2000106374A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>LANG THOMAS DR</creatorcontrib><creatorcontrib>ZELLER HANS RUDOLF DR</creatorcontrib><title>INSULATED GATE BIPOLAR TRANSISTOR MODULE HAVING RESISTANCE TO SHORT-CIRCUITING</title><description>PROBLEM TO BE SOLVED: To prevent short-circuit of individual chips from causing damages to the entire module, by forming an eutectic mixed material of a layer which is joined to main electrodes of a silicon semiconductor and which contains silver and silicon. SOLUTION: Semiconductor chips 4 have main electrodes 5 and 6 which are coated with metal on both of tops and bottoms, and are electrically connected. The semiconductor chips 4 are supported on a conductive substrate 2, and connection pistons are arranged directly on every chips. A layer 7 arranged between the metal joining surfaces adjacent to either the main electrode 5 or the main electrode 6 is easily manufactured from a thin metal chip containing silver, or is applied to the main electrodes as paste. Usually, the thickness of the layer 7 is set to a half or larger than that of the semiconductor chip 4. Silver is suitable for the semiconductor 4 as a mating material of an eutectic material. The eutectic point of AgSi containing silver of 11% by the atomic weight is 835 deg.C, and this is far lower than the melting point of simple substance of silicon.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2000</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZPDz9AsO9XEMcXVRcAeSCk6eAf4-jkEKIUGOfsGewSH-QQq-_i6hPq4KHo5hnn7uCkGuIGFHP2dXhRB_hWAP_6AQXWfPIOdQzxCgNA8Da1piTnEqL5TmZlBycw1x9tBNLciPTy0uSExOzUstifcKMDIwMDA0MDM2N3E0JkoRAKKpL0g</recordid><startdate>20000411</startdate><enddate>20000411</enddate><creator>LANG THOMAS DR</creator><creator>ZELLER HANS RUDOLF DR</creator><scope>EVB</scope></search><sort><creationdate>20000411</creationdate><title>INSULATED GATE BIPOLAR TRANSISTOR MODULE HAVING RESISTANCE TO SHORT-CIRCUITING</title><author>LANG THOMAS DR ; ZELLER HANS RUDOLF DR</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2000106374A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2000</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>LANG THOMAS DR</creatorcontrib><creatorcontrib>ZELLER HANS RUDOLF DR</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>LANG THOMAS DR</au><au>ZELLER HANS RUDOLF DR</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>INSULATED GATE BIPOLAR TRANSISTOR MODULE HAVING RESISTANCE TO SHORT-CIRCUITING</title><date>2000-04-11</date><risdate>2000</risdate><abstract>PROBLEM TO BE SOLVED: To prevent short-circuit of individual chips from causing damages to the entire module, by forming an eutectic mixed material of a layer which is joined to main electrodes of a silicon semiconductor and which contains silver and silicon. SOLUTION: Semiconductor chips 4 have main electrodes 5 and 6 which are coated with metal on both of tops and bottoms, and are electrically connected. The semiconductor chips 4 are supported on a conductive substrate 2, and connection pistons are arranged directly on every chips. A layer 7 arranged between the metal joining surfaces adjacent to either the main electrode 5 or the main electrode 6 is easily manufactured from a thin metal chip containing silver, or is applied to the main electrodes as paste. Usually, the thickness of the layer 7 is set to a half or larger than that of the semiconductor chip 4. Silver is suitable for the semiconductor 4 as a mating material of an eutectic material. The eutectic point of AgSi containing silver of 11% by the atomic weight is 835 deg.C, and this is far lower than the melting point of simple substance of silicon.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | INSULATED GATE BIPOLAR TRANSISTOR MODULE HAVING RESISTANCE TO SHORT-CIRCUITING |
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