INSULATED GATE BIPOLAR TRANSISTOR MODULE HAVING RESISTANCE TO SHORT-CIRCUITING

PROBLEM TO BE SOLVED: To prevent short-circuit of individual chips from causing damages to the entire module, by forming an eutectic mixed material of a layer which is joined to main electrodes of a silicon semiconductor and which contains silver and silicon. SOLUTION: Semiconductor chips 4 have mai...

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Bibliographische Detailangaben
Hauptverfasser: LANG THOMAS DR, ZELLER HANS RUDOLF DR
Format: Patent
Sprache:eng
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Zusammenfassung:PROBLEM TO BE SOLVED: To prevent short-circuit of individual chips from causing damages to the entire module, by forming an eutectic mixed material of a layer which is joined to main electrodes of a silicon semiconductor and which contains silver and silicon. SOLUTION: Semiconductor chips 4 have main electrodes 5 and 6 which are coated with metal on both of tops and bottoms, and are electrically connected. The semiconductor chips 4 are supported on a conductive substrate 2, and connection pistons are arranged directly on every chips. A layer 7 arranged between the metal joining surfaces adjacent to either the main electrode 5 or the main electrode 6 is easily manufactured from a thin metal chip containing silver, or is applied to the main electrodes as paste. Usually, the thickness of the layer 7 is set to a half or larger than that of the semiconductor chip 4. Silver is suitable for the semiconductor 4 as a mating material of an eutectic material. The eutectic point of AgSi containing silver of 11% by the atomic weight is 835 deg.C, and this is far lower than the melting point of simple substance of silicon.