STADIO AD ALTA RESISTENZA D'USCITA IN TECNOLOGIA MOS,PARTICOLARMENTE PER CIRCUITI INTEGRATI
A first N-channel transistor (M1) and a second N-channel transistor (M2) are cascode connected and the source electrode of the first transistor is connected to the ground; a third P-channel transistor (M3) and a fourth P-channel transistor (M4) are also cascode connected, and the source of the fourt...
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| creator | DEVECCHI DANIELE TORELLI GUIDO |
| description | A first N-channel transistor (M1) and a second N-channel transistor (M2) are cascode connected and the source electrode of the first transistor is connected to the ground; a third P-channel transistor (M3) and a fourth P-channel transistor (M4) are also cascode connected, and the source of the fourth transistor is connected to a supply voltage; the drains of the second and third transistors (M2, M3) are mutually connected to act as output terminal. According to the invention, the absolute values of the threshold voltages of the second and third transistors are lower than the threshold voltages of the first and fourth transistors, and the gates of the first and second transistors are furthermore mutually connected to act as input terminal for a voltage signal, while the gates of said third and fourth transistors are mutually connected to act as input terminal for a bias voltage. |
| format | Patent |
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According to the invention, the absolute values of the threshold voltages of the second and third transistors are lower than the threshold voltages of the first and fourth transistors, and the gates of the first and second transistors are furthermore mutually connected to act as input terminal for a voltage signal, while the gates of said third and fourth transistors are mutually connected to act as input terminal for a bias voltage.</description><language>ita</language><subject>AMPLIFIERS ; BASIC ELECTRONIC CIRCUITRY ; ELECTRICITY</subject><creationdate>1990</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19900322&DB=EPODOC&CC=IT&NR=1217373B$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25568,76551</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19900322&DB=EPODOC&CC=IT&NR=1217373B$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>DEVECCHI DANIELE</creatorcontrib><creatorcontrib>TORELLI GUIDO</creatorcontrib><title>STADIO AD ALTA RESISTENZA D'USCITA IN TECNOLOGIA MOS,PARTICOLARMENTE PER CIRCUITI INTEGRATI</title><description>A first N-channel transistor (M1) and a second N-channel transistor (M2) are cascode connected and the source electrode of the first transistor is connected to the ground; a third P-channel transistor (M3) and a fourth P-channel transistor (M4) are also cascode connected, and the source of the fourth transistor is connected to a supply voltage; the drains of the second and third transistors (M2, M3) are mutually connected to act as output terminal. According to the invention, the absolute values of the threshold voltages of the second and third transistors are lower than the threshold voltages of the first and fourth transistors, and the gates of the first and second transistors are furthermore mutually connected to act as input terminal for a voltage signal, while the gates of said third and fourth transistors are mutually connected to act as input terminal for a bias voltage.</description><subject>AMPLIFIERS</subject><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRICITY</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1990</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqFyrEKwjAQgOEuDqI-g7e56FAzdD4vZz1Ik5JcFx1KkTiJFur7Ywd3px9-vmVxS4pWAqAFdIoQOUlS9lcEu-sSyfzEgzL54EItCE1I-xajCgWHsWGvDC1HIInUicrMleuIKuti8RieU978uiq2Z1a6HPL47vM0Dvf8yp9etDyWlanMyfwXX7vWMVo</recordid><startdate>19900322</startdate><enddate>19900322</enddate><creator>DEVECCHI DANIELE</creator><creator>TORELLI GUIDO</creator><scope>EVB</scope></search><sort><creationdate>19900322</creationdate><title>STADIO AD ALTA RESISTENZA D'USCITA IN TECNOLOGIA MOS,PARTICOLARMENTE PER CIRCUITI INTEGRATI</title><author>DEVECCHI DANIELE ; TORELLI GUIDO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_IT1217373B3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>ita</language><creationdate>1990</creationdate><topic>AMPLIFIERS</topic><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>ELECTRICITY</topic><toplevel>online_resources</toplevel><creatorcontrib>DEVECCHI DANIELE</creatorcontrib><creatorcontrib>TORELLI GUIDO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>DEVECCHI DANIELE</au><au>TORELLI GUIDO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>STADIO AD ALTA RESISTENZA D'USCITA IN TECNOLOGIA MOS,PARTICOLARMENTE PER CIRCUITI INTEGRATI</title><date>1990-03-22</date><risdate>1990</risdate><abstract>A first N-channel transistor (M1) and a second N-channel transistor (M2) are cascode connected and the source electrode of the first transistor is connected to the ground; a third P-channel transistor (M3) and a fourth P-channel transistor (M4) are also cascode connected, and the source of the fourth transistor is connected to a supply voltage; the drains of the second and third transistors (M2, M3) are mutually connected to act as output terminal. According to the invention, the absolute values of the threshold voltages of the second and third transistors are lower than the threshold voltages of the first and fourth transistors, and the gates of the first and second transistors are furthermore mutually connected to act as input terminal for a voltage signal, while the gates of said third and fourth transistors are mutually connected to act as input terminal for a bias voltage.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | AMPLIFIERS BASIC ELECTRONIC CIRCUITRY ELECTRICITY |
| title | STADIO AD ALTA RESISTENZA D'USCITA IN TECNOLOGIA MOS,PARTICOLARMENTE PER CIRCUITI INTEGRATI |
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