Neural network processing

Neural network processing

Conflict-free, stall-free, broadcast networks on neural inference chips are provided. In various embodiments, a neural inference chip comprises a plurality of network nodes and a network on chip interconnecting the plurality of network nodes. The network comprises at least one pair of directional pa...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Andrew Stephen Cassidy, Michael Vincent DeBole, John Vernon Arthur, Pallab Datta, Rathinakumar Appuswamy, Jun Sawada, Dharmendra S. Modha, Tapan Kumar Nayak
Format: Patent
Sprache:eng ; heb
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator Andrew Stephen Cassidy
Michael Vincent DeBole
John Vernon Arthur
Pallab Datta
Rathinakumar Appuswamy
Jun Sawada
Dharmendra S. Modha
Tapan Kumar Nayak
description Conflict-free, stall-free, broadcast networks on neural inference chips are provided. In various embodiments, a neural inference chip comprises a plurality of network nodes and a network on chip interconnecting the plurality of network nodes. The network comprises at least one pair of directional paths. The paths of each pair have opposite directions and a common end. The network is configured to accept data at any of the plurality of nodes. The network is configured to propagate data along a first of the pair of directional paths from a source node to the common end of the pair of directional paths and along a second of the pair of directional paths from the common end of the pair of directional paths to one or more destination node.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_IL301198A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>IL301198A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_IL301198A3</originalsourceid><addsrcrecordid>eNrjZJD0Sy0tSsxRyEstKc8vylYoKMpPTi0uzsxL52FgTUvMKU7lhdLcDHJuriHOHrqpBfnxqcUFicmpQE3xnj7GBoaGlhaOxgQVAAB1_CG8</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Neural network processing</title><source>esp@cenet</source><creator>Andrew Stephen Cassidy ; Michael Vincent DeBole ; John Vernon Arthur ; Pallab Datta ; Rathinakumar Appuswamy ; Jun Sawada ; Dharmendra S. Modha ; Tapan Kumar Nayak</creator><creatorcontrib>Andrew Stephen Cassidy ; Michael Vincent DeBole ; John Vernon Arthur ; Pallab Datta ; Rathinakumar Appuswamy ; Jun Sawada ; Dharmendra S. Modha ; Tapan Kumar Nayak</creatorcontrib><description>Conflict-free, stall-free, broadcast networks on neural inference chips are provided. In various embodiments, a neural inference chip comprises a plurality of network nodes and a network on chip interconnecting the plurality of network nodes. The network comprises at least one pair of directional paths. The paths of each pair have opposite directions and a common end. The network is configured to accept data at any of the plurality of nodes. The network is configured to propagate data along a first of the pair of directional paths from a source node to the common end of the pair of directional paths and along a second of the pair of directional paths from the common end of the pair of directional paths to one or more destination node.</description><language>eng ; heb</language><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20230501&amp;DB=EPODOC&amp;CC=IL&amp;NR=301198A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20230501&amp;DB=EPODOC&amp;CC=IL&amp;NR=301198A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Andrew Stephen Cassidy</creatorcontrib><creatorcontrib>Michael Vincent DeBole</creatorcontrib><creatorcontrib>John Vernon Arthur</creatorcontrib><creatorcontrib>Pallab Datta</creatorcontrib><creatorcontrib>Rathinakumar Appuswamy</creatorcontrib><creatorcontrib>Jun Sawada</creatorcontrib><creatorcontrib>Dharmendra S. Modha</creatorcontrib><creatorcontrib>Tapan Kumar Nayak</creatorcontrib><title>Neural network processing</title><description>Conflict-free, stall-free, broadcast networks on neural inference chips are provided. In various embodiments, a neural inference chip comprises a plurality of network nodes and a network on chip interconnecting the plurality of network nodes. The network comprises at least one pair of directional paths. The paths of each pair have opposite directions and a common end. The network is configured to accept data at any of the plurality of nodes. The network is configured to propagate data along a first of the pair of directional paths from a source node to the common end of the pair of directional paths and along a second of the pair of directional paths from the common end of the pair of directional paths to one or more destination node.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJD0Sy0tSsxRyEstKc8vylYoKMpPTi0uzsxL52FgTUvMKU7lhdLcDHJuriHOHrqpBfnxqcUFicmpQE3xnj7GBoaGlhaOxgQVAAB1_CG8</recordid><startdate>20230501</startdate><enddate>20230501</enddate><creator>Andrew Stephen Cassidy</creator><creator>Michael Vincent DeBole</creator><creator>John Vernon Arthur</creator><creator>Pallab Datta</creator><creator>Rathinakumar Appuswamy</creator><creator>Jun Sawada</creator><creator>Dharmendra S. Modha</creator><creator>Tapan Kumar Nayak</creator><scope>EVB</scope></search><sort><creationdate>20230501</creationdate><title>Neural network processing</title><author>Andrew Stephen Cassidy ; Michael Vincent DeBole ; John Vernon Arthur ; Pallab Datta ; Rathinakumar Appuswamy ; Jun Sawada ; Dharmendra S. Modha ; Tapan Kumar Nayak</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_IL301198A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; heb</language><creationdate>2023</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Andrew Stephen Cassidy</creatorcontrib><creatorcontrib>Michael Vincent DeBole</creatorcontrib><creatorcontrib>John Vernon Arthur</creatorcontrib><creatorcontrib>Pallab Datta</creatorcontrib><creatorcontrib>Rathinakumar Appuswamy</creatorcontrib><creatorcontrib>Jun Sawada</creatorcontrib><creatorcontrib>Dharmendra S. Modha</creatorcontrib><creatorcontrib>Tapan Kumar Nayak</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Andrew Stephen Cassidy</au><au>Michael Vincent DeBole</au><au>John Vernon Arthur</au><au>Pallab Datta</au><au>Rathinakumar Appuswamy</au><au>Jun Sawada</au><au>Dharmendra S. Modha</au><au>Tapan Kumar Nayak</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Neural network processing</title><date>2023-05-01</date><risdate>2023</risdate><abstract>Conflict-free, stall-free, broadcast networks on neural inference chips are provided. In various embodiments, a neural inference chip comprises a plurality of network nodes and a network on chip interconnecting the plurality of network nodes. The network comprises at least one pair of directional paths. The paths of each pair have opposite directions and a common end. The network is configured to accept data at any of the plurality of nodes. The network is configured to propagate data along a first of the pair of directional paths from a source node to the common end of the pair of directional paths and along a second of the pair of directional paths from the common end of the pair of directional paths to one or more destination node.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng ; heb
recordid cdi_epo_espacenet_IL301198A
source esp@cenet
title Neural network processing
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-07T19%3A03%3A04IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Andrew%20Stephen%20Cassidy&rft.date=2023-05-01&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EIL301198A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true