Computer architecture and processing
The invention is a computer architecture comprising a central processing device adapted for processing a data stream (40) consisting of data elements and comprising an instruction array and a data array. Said central processing device comprising at least one array of processing units (30, 32) connec...
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| creator | RAK ADAM CSEREY GYOERGY GABOR |
| description | The invention is a computer architecture comprising a central processing device adapted for processing a data stream (40) consisting of data elements and comprising an instruction array and a data array. Said central processing device comprising at least one array of processing units (30, 32) connected to each other and being capable of executing an operation on the data array based on the instruction array, and data transferring elements connected to the outermost processing units (30, 32) of the at least one array of the processing units (30, 32) and adapted for transferring the data stream (40). The computer architecture further comprises at least one data storage device connected to the central processing device and an instruction definition device adapted for defining an instruction array implementing a computer program on the architecture and determining the traverse route (31) of the data stream (40), said instruction definition device is connected to the central processing device, and the data storage device comprises a storage unit adapted for storing the data stream (40), and a sorting unit adapted for reordering the data elements. The invention is furthermore a processing method. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_HUP1300561A2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>HUP1300561A2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_HUP1300561A23</originalsourceid><addsrcrecordid>eNrjZFBxzs8tKC1JLVJILErOyCxJTS4pLUpVSMxLUSgoyk9OLS7OzEvnYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQWJyal5qSXxHqEBhsYGBqZmho5GxsSoAQBBMydp</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Computer architecture and processing</title><source>esp@cenet</source><creator>RAK ADAM ; CSEREY GYOERGY GABOR</creator><creatorcontrib>RAK ADAM ; CSEREY GYOERGY GABOR</creatorcontrib><description>The invention is a computer architecture comprising a central processing device adapted for processing a data stream (40) consisting of data elements and comprising an instruction array and a data array. Said central processing device comprising at least one array of processing units (30, 32) connected to each other and being capable of executing an operation on the data array based on the instruction array, and data transferring elements connected to the outermost processing units (30, 32) of the at least one array of the processing units (30, 32) and adapted for transferring the data stream (40). The computer architecture further comprises at least one data storage device connected to the central processing device and an instruction definition device adapted for defining an instruction array implementing a computer program on the architecture and determining the traverse route (31) of the data stream (40), said instruction definition device is connected to the central processing device, and the data storage device comprises a storage unit adapted for storing the data stream (40), and a sorting unit adapted for reordering the data elements. The invention is furthermore a processing method.</description><language>eng ; hun</language><creationdate>2015</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20150330&DB=EPODOC&CC=HU&NR=P1300561A2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76318</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20150330&DB=EPODOC&CC=HU&NR=P1300561A2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>RAK ADAM</creatorcontrib><creatorcontrib>CSEREY GYOERGY GABOR</creatorcontrib><title>Computer architecture and processing</title><description>The invention is a computer architecture comprising a central processing device adapted for processing a data stream (40) consisting of data elements and comprising an instruction array and a data array. Said central processing device comprising at least one array of processing units (30, 32) connected to each other and being capable of executing an operation on the data array based on the instruction array, and data transferring elements connected to the outermost processing units (30, 32) of the at least one array of the processing units (30, 32) and adapted for transferring the data stream (40). The computer architecture further comprises at least one data storage device connected to the central processing device and an instruction definition device adapted for defining an instruction array implementing a computer program on the architecture and determining the traverse route (31) of the data stream (40), said instruction definition device is connected to the central processing device, and the data storage device comprises a storage unit adapted for storing the data stream (40), and a sorting unit adapted for reordering the data elements. The invention is furthermore a processing method.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2015</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFBxzs8tKC1JLVJILErOyCxJTS4pLUpVSMxLUSgoyk9OLS7OzEvnYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQWJyal5qSXxHqEBhsYGBqZmho5GxsSoAQBBMydp</recordid><startdate>20150330</startdate><enddate>20150330</enddate><creator>RAK ADAM</creator><creator>CSEREY GYOERGY GABOR</creator><scope>EVB</scope></search><sort><creationdate>20150330</creationdate><title>Computer architecture and processing</title><author>RAK ADAM ; CSEREY GYOERGY GABOR</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_HUP1300561A23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; hun</language><creationdate>2015</creationdate><toplevel>online_resources</toplevel><creatorcontrib>RAK ADAM</creatorcontrib><creatorcontrib>CSEREY GYOERGY GABOR</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>RAK ADAM</au><au>CSEREY GYOERGY GABOR</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Computer architecture and processing</title><date>2015-03-30</date><risdate>2015</risdate><abstract>The invention is a computer architecture comprising a central processing device adapted for processing a data stream (40) consisting of data elements and comprising an instruction array and a data array. Said central processing device comprising at least one array of processing units (30, 32) connected to each other and being capable of executing an operation on the data array based on the instruction array, and data transferring elements connected to the outermost processing units (30, 32) of the at least one array of the processing units (30, 32) and adapted for transferring the data stream (40). The computer architecture further comprises at least one data storage device connected to the central processing device and an instruction definition device adapted for defining an instruction array implementing a computer program on the architecture and determining the traverse route (31) of the data stream (40), said instruction definition device is connected to the central processing device, and the data storage device comprises a storage unit adapted for storing the data stream (40), and a sorting unit adapted for reordering the data elements. The invention is furthermore a processing method.</abstract><oa>free_for_read</oa></addata></record> |
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| language | eng ; hun |
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| title | Computer architecture and processing |
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