Improvements relating to matrix storage devices

859,846. Electric digital-data-storage apparatus. ELECTRIC & MUSICAL INDUSTRIES Ltd. March 22, 1957 [April 4, 1956], No. 10237/56. Class 106 (1). A storage device comprises a matrix of storage elements, means for applying thereto data signals to be stored, and means for applying sequentially to the rows of elements read-out signals to reproduce the stored data signals the arrangement being such that only particular rows are read out to a given destination. In a first embodiment the six columns of a matrix, Fig. 1, are identified with a six-element binarydecimal, alpha-numeric code. Entry of codeddecimal digits is from a buffer store 2 in response to a control signal on line 3; a corresponding magnetic representation is set up in the cores C of any row of the matrix which at the same time is sensitized by a read-in pulse on the respective X control circuit. When read-out pulses are applied in sequence to the X control circuits X1 to X10 the output signals are distributed to various output registers R1, R2, R3 in accordance with a pre-arranged scheme. As shown, rows 1 to 4 and 10 of the matrix are read out to register R1, rows 5 to 7 to register R2, rows 8 and 9 to register R3, and so on. Such arrangements are intended for built-in sub-routines in a computer. In another embodiment an extra column of cores Cp, Fig. 2, is employed. The output register R1 is insensitive to signals on the read-out lines D11 to D16 unless it receives a pulse from gate 7 simultaneously. This only occurs when the row being stimulated by an X-read-out pulse includes a Cp core in the " 1 " state. In another embodiment a counter 9, Fig. 3, opens in succession gates 13, 15, 17 routing information from the matrix SM in accordance with a prearranged scheme. The counter is stepped on each time an X-signal finds a Cp core in the " 1 " state and is returned to zero when the last row of the matrix has been read out. In another embodiment (Fig. 4, not shown) two columns of Cp cores are provided, one controlling a switch permitting output signals to pass through the read-out register of the matrix and the other controlling a switch inhibiting read-out of signals. The switches are cross-connected to form a trigger pair. In another embodiment a series of matrices of the type shown in Fig. 2 are each associated with an additional " skip core Cs, Fig. 5. A shift register 24 controls the sequence of read-out signals on the X lines of each matrix while a second shift register 20 determines which mat