Accessing topological mapping of cores

A method, computer program product, and system include a processor(s) issues an instruction that includes processing core information that includes locations of processing cores of the computing system (logical cores and/or physical cores), and an operator selection. The processor(s) sets security p...

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Hauptverfasser: Seth Lederer, Peter Dana Driever, Brian Keith Wade, Omkar Ulhas Javeri
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creator Seth Lederer
Peter Dana Driever
Brian Keith Wade
Omkar Ulhas Javeri
description A method, computer program product, and system include a processor(s) issues an instruction that includes processing core information that includes locations of processing cores of the computing system (logical cores and/or physical cores), and an operator selection. The processor(s) sets security parameters for information returned by the instruction which is topological information for mapping of the logical cores to the physical cores. The processor(s) obtains the topological information and utilizes an operating system to map the logical cores to the physical cores.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_GB2624327B</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>GB2624327B</sourcerecordid><originalsourceid>FETCH-epo_espacenet_GB2624327B3</originalsourceid><addsrcrecordid>eNrjZFBzTE5OLS7OzEtXKMkvyM_JT89MTsxRyE0sKACJ5acpJOcXpRbzMLCmJeYUp_JCaW4GeTfXEGcP3dSC_PjU4oLE5NS81JJ4dycjMyMTYyNzJ2PCKgDe-ia5</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Accessing topological mapping of cores</title><source>esp@cenet</source><creator>Seth Lederer ; Peter Dana Driever ; Brian Keith Wade ; Omkar Ulhas Javeri</creator><creatorcontrib>Seth Lederer ; Peter Dana Driever ; Brian Keith Wade ; Omkar Ulhas Javeri</creatorcontrib><description>A method, computer program product, and system include a processor(s) issues an instruction that includes processing core information that includes locations of processing cores of the computing system (logical cores and/or physical cores), and an operator selection. The processor(s) sets security parameters for information returned by the instruction which is topological information for mapping of the logical cores to the physical cores. The processor(s) obtains the topological information and utilizes an operating system to map the logical cores to the physical cores.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20241016&amp;DB=EPODOC&amp;CC=GB&amp;NR=2624327B$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20241016&amp;DB=EPODOC&amp;CC=GB&amp;NR=2624327B$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Seth Lederer</creatorcontrib><creatorcontrib>Peter Dana Driever</creatorcontrib><creatorcontrib>Brian Keith Wade</creatorcontrib><creatorcontrib>Omkar Ulhas Javeri</creatorcontrib><title>Accessing topological mapping of cores</title><description>A method, computer program product, and system include a processor(s) issues an instruction that includes processing core information that includes locations of processing cores of the computing system (logical cores and/or physical cores), and an operator selection. The processor(s) sets security parameters for information returned by the instruction which is topological information for mapping of the logical cores to the physical cores. The processor(s) obtains the topological information and utilizes an operating system to map the logical cores to the physical cores.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFBzTE5OLS7OzEtXKMkvyM_JT89MTsxRyE0sKACJ5acpJOcXpRbzMLCmJeYUp_JCaW4GeTfXEGcP3dSC_PjU4oLE5NS81JJ4dycjMyMTYyNzJ2PCKgDe-ia5</recordid><startdate>20241016</startdate><enddate>20241016</enddate><creator>Seth Lederer</creator><creator>Peter Dana Driever</creator><creator>Brian Keith Wade</creator><creator>Omkar Ulhas Javeri</creator><scope>EVB</scope></search><sort><creationdate>20241016</creationdate><title>Accessing topological mapping of cores</title><author>Seth Lederer ; Peter Dana Driever ; Brian Keith Wade ; Omkar Ulhas Javeri</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_GB2624327B3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>Seth Lederer</creatorcontrib><creatorcontrib>Peter Dana Driever</creatorcontrib><creatorcontrib>Brian Keith Wade</creatorcontrib><creatorcontrib>Omkar Ulhas Javeri</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Seth Lederer</au><au>Peter Dana Driever</au><au>Brian Keith Wade</au><au>Omkar Ulhas Javeri</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Accessing topological mapping of cores</title><date>2024-10-16</date><risdate>2024</risdate><abstract>A method, computer program product, and system include a processor(s) issues an instruction that includes processing core information that includes locations of processing cores of the computing system (logical cores and/or physical cores), and an operator selection. The processor(s) sets security parameters for information returned by the instruction which is topological information for mapping of the logical cores to the physical cores. The processor(s) obtains the topological information and utilizes an operating system to map the logical cores to the physical cores.</abstract><oa>free_for_read</oa></addata></record>
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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title Accessing topological mapping of cores
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-23T09%3A09%3A02IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Seth%20Lederer&rft.date=2024-10-16&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EGB2624327B%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true