Systems and methods for access protection of system peripherals
A system may include a plurality of processing cores, a target shared among the plurality of processing cores and coupled to the plurality of processing cores via a shared bus, and access control logic configured to, based on access configuration settings associated with the target, control access o...
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| creator | Younes Djadi Nathan Buchanan Nariankadu D Hemkumar Xingdong Dai |
| description | A system may include a plurality of processing cores, a target shared among the plurality of processing cores and coupled to the plurality of processing cores via a shared bus, and access control logic configured to, based on access configuration settings associated with the target, control access of requests from each of the plurality of processing cores based on a privilege level of each of the plurality of processing cores, in order to dynamically allocate and re-allocate the target among the plurality of processing cores in accordance with the privilege levels and to dynamically utilize the target in accordance with the privilege levels. |
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Nathan Buchanan ; Nariankadu D Hemkumar ; Xingdong Dai</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_GB2624257B3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2024</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>Younes Djadi</creatorcontrib><creatorcontrib>Nathan Buchanan</creatorcontrib><creatorcontrib>Nariankadu D Hemkumar</creatorcontrib><creatorcontrib>Xingdong Dai</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Younes Djadi</au><au>Nathan Buchanan</au><au>Nariankadu D Hemkumar</au><au>Xingdong Dai</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Systems and methods for access protection of system peripherals</title><date>2024-11-06</date><risdate>2024</risdate><abstract>A system may include a plurality of processing cores, a target shared among the plurality of processing cores and coupled to the plurality of processing cores via a shared bus, and access control logic configured to, based on access configuration settings associated with the target, control access of requests from each of the plurality of processing cores based on a privilege level of each of the plurality of processing cores, in order to dynamically allocate and re-allocate the target among the plurality of processing cores in accordance with the privilege levels and to dynamically utilize the target in accordance with the privilege levels.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | Systems and methods for access protection of system peripherals |
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