Synchronised multi-processor operating system timer

An integrated-circuit device (1, fig. 1) comprises a plurality of processor cores (2, 3, fig 1) and a system timer 10. The system timer includes a first oscillator 32 that outputs a first clock signal at a first frequency, a first counter register 34 incremented by the first clock signal and a plurality of event registers 52. Each event register triggers an event when a value held therein is determined to be equal to a value held in the first counter register. The first counter register is readable by each of the plurality of processor cores, and each of the processor cores are capable of writing to at least one of the event registers.