Central scheduler and instruction dispatcher for a neural inference processor

Neural inference processors are provided. In various embodiments, a processor includes a plurality of cores. Each core includes a neural computation unit, an activation memory, and a local controller. The neural computation unit is adapted to apply a plurality of synaptic weights to a plurality of i...

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Bibliographische Detailangaben

Hauptverfasser:	Andrew Stephen Cassidy, Pallab Datta, Dharmendra Shantilal Modha, Hartmut Penner, Jennifer Klamo, Rathinakumar Appuswamy, Steven Kyle Esser, Jun Sawada, John Vernon` Arthur, Brian Seisho Taba, Myron Dale Flickner
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS COMPUTING COUNTING PHYSICS
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