High durability solder terminals

An electronic device package includes a lower surface for conducting electronic signals, a first solder bond pad having a first size disposed on the lower surface, and a plurality of second solder bond pads having second sizes smaller than the first size disposed on the lower surface and surrounding...

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Hauptverfasser: Toru Yamaji, Yuji Yashiro
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Sprache:eng
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creator Toru Yamaji
Yuji Yashiro
description An electronic device package includes a lower surface for conducting electronic signals, a first solder bond pad having a first size disposed on the lower surface, and a plurality of second solder bond pads having second sizes smaller than the first size disposed on the lower surface and surrounding the first solder bond pad.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_GB2583552B</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>GB2583552B</sourcerecordid><originalsourceid>FETCH-epo_espacenet_GB2583552B3</originalsourceid><addsrcrecordid>eNrjZFDwyEzPUEgpLUpMyszJLKlUKM7PSUktUihJLcrNzEvMKeZhYE0DUqm8UJqbQd7NNcTZQze1ID8-tbggMTk1L7Uk3t3JyNTC2NTUyMmYsAoA1xEkog</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>High durability solder terminals</title><source>esp@cenet</source><creator>Toru Yamaji ; Yuji Yashiro</creator><creatorcontrib>Toru Yamaji ; Yuji Yashiro</creatorcontrib><description>An electronic device package includes a lower surface for conducting electronic signals, a first solder bond pad having a first size disposed on the lower surface, and a plurality of second solder bond pads having second sizes smaller than the first size disposed on the lower surface and surrounding the first solder bond pad.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; BASIC ELECTRONIC CIRCUITRY ; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; PRINTED CIRCUITS ; RESONATORS ; SEMICONDUCTOR DEVICES</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20221221&amp;DB=EPODOC&amp;CC=GB&amp;NR=2583552B$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76516</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20221221&amp;DB=EPODOC&amp;CC=GB&amp;NR=2583552B$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Toru Yamaji</creatorcontrib><creatorcontrib>Yuji Yashiro</creatorcontrib><title>High durability solder terminals</title><description>An electronic device package includes a lower surface for conducting electronic signals, a first solder bond pad having a first size disposed on the lower surface, and a plurality of second solder bond pads having second sizes smaller than the first size disposed on the lower surface and surrounding the first solder bond pad.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>PRINTED CIRCUITS</subject><subject>RESONATORS</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFDwyEzPUEgpLUpMyszJLKlUKM7PSUktUihJLcrNzEvMKeZhYE0DUqm8UJqbQd7NNcTZQze1ID8-tbggMTk1L7Uk3t3JyNTC2NTUyMmYsAoA1xEkog</recordid><startdate>20221221</startdate><enddate>20221221</enddate><creator>Toru Yamaji</creator><creator>Yuji Yashiro</creator><scope>EVB</scope></search><sort><creationdate>20221221</creationdate><title>High durability solder terminals</title><author>Toru Yamaji ; Yuji Yashiro</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_GB2583552B3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2022</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>PRINTED CIRCUITS</topic><topic>RESONATORS</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Toru Yamaji</creatorcontrib><creatorcontrib>Yuji Yashiro</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Toru Yamaji</au><au>Yuji Yashiro</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>High durability solder terminals</title><date>2022-12-21</date><risdate>2022</risdate><abstract>An electronic device package includes a lower surface for conducting electronic signals, a first solder bond pad having a first size disposed on the lower surface, and a plurality of second solder bond pads having second sizes smaller than the first size disposed on the lower surface and surrounding the first solder bond pad.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
BASIC ELECTRONIC CIRCUITRY
CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS
MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
PRINTED CIRCUITS
RESONATORS
SEMICONDUCTOR DEVICES
title High durability solder terminals
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-19T20%3A46%3A41IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Toru%20Yamaji&rft.date=2022-12-21&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EGB2583552B%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true