Systems, apparatuses, and methods for blending two source operands into a single destination using a writemask

A blend instruction is performed on a first plurality of elements A0-A15 stored in a first 512 bit source vector register and a second plurality of elements B0-B15 stored in a second 512 bit vector register. Each value in the first plurality of elements has a corresponding value in the second plurality of elements and a corresponding predicate data bit in a mask, wherein the mask bit controls which of the source vector elements is written to the destination vector register. The blend operation is performed by a chip comprising a first processor, second processor, a graphics processor and an integrated memory controller.